Selective germanium P-contact metalization through trench

Patent metadata

Field	Value
Publication number	US-10879353-B2
Application number	US-201916722855-A
Country	US
Kind code	B2
Filing date	Dec 20, 2019
Priority date	Dec 21, 2010
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a fin comprising silicon;
a gate electrode over the fin, the gate electrode having a first side, and the gate electrode having a second side opposite the first side;
a first dielectric spacer along the first side of the gate electrode;
a first source or drain region in the fin proximate the first side of the gate electrode, a portion of the first source or drain region beneath the first dielectric spacer, wherein the first source or drain region comprises a concentration of germanium in excess of 50%, the first source or drain region comprises a boron concentration in excess of 1E20, and the first source or drain region comprises two or more facets and a top surface;
a second dielectric spacer along the second side of the gate electrode;
a second source or drain region in the fin proximate the second side of the gate electrode, a portion of the second source or drain region beneath the second dielectric spacer, wherein the second source or drain region comprises a concentration of germanium in excess of 50%, the second source or drain region comprises a boron concentration in excess of 1E20, and the second source or drain region comprises two or more facets and a top surface;
a dielectric layer over the first source or drain region and over the second source or drain region, the dielectric layer having a first opening exposing only a portion of the first source or drain region, and the dielectric layer having a second opening exposing only a portion of the second source or drain region;
a contact metal in the first opening and on the first source or drain region, and the contact metal in the second opening and on the second source or drain region, the contact metal comprising titanium and silicon;
a first contact plug in the first opening on the contact metal; and
a second contact plug in the second opening on the contact metal.

2. The integrated circuit structure of claim 1 , further comprising:
an isolation region, wherein the fin protrudes through the isolation region, and wherein a portion of the gate electrode, a portion of the first dielectric spacer, and a portion of the second dielectric spacer are over the isolation region.

3. The integrated circuit structure of claim 1 , further comprising:
a gate dielectric layer, wherein the gate electrode is on the gate dielectric layer, wherein the gate dielectric layer comprises a high-k dielectric material, and wherein the gate electrode comprises a metal layer.

4. The integrated circuit structure of claim 1 , wherein the first source or drain region comprises three or more facets, and the second source or drain region comprises three or more facets.

5. The integrated circuit structure of claim 1 , wherein the first source or drain region comprises four or more facets, and the second source or drain region comprises four or more facets.

6. The integrated circuit structure of claim 1 , wherein the first source or drain region comprises a boron concentration in excess of 5E20, and wherein the second source or drain region comprises a boron concentration in excess of 5E20.

7. The integrated circuit structure of claim 1 , wherein the first source or drain region comprises a boron concentration in excess of 2E21, and wherein the second source or drain region comprises a boron concentration in excess of 2E21.

8. An integrated circuit structure, comprising:
a body comprising silicon;
a gate electrode over the body, the gate electrode having a first side, and the gate electrode having a second side opposite the first side;
a first dielectric spacer along the first side of the gate electrode;
a first source or drain region in the body proximate the first side of the gate electrode, a portion of the first source or drain region beneath the first dielectric spacer, wherein the first source or drain region comprises a concentration of germanium in excess of 50%, the first source or drain region comprises a boron concentration in excess of 1E20, and the first source or drain region comprises two or more facets and a top surface;
a second dielectric spacer along the second side of the gate electrode;
a second source or drain region in the body proximate the second side of the gate electrode, a portion of the second source or drain region beneath the second dielectric spacer, wherein the second source or drain region comprises a concentration of germanium in excess of 50%, the second source or drain region comprises a boron concentration in excess of 1E20, and the second source or drain region comprises two or more facets and a top surface;
a dielectric layer over the first source or drain region and over the second source or drain region, the dielectric layer having a first opening exposing only a portion of the first source or drain region, and the dielectric layer having a second opening exposing only a portion of the second source or drain region;
a contact metal in the first opening and on the first source or drain region, and the contact metal in the second opening and on the second source or drain region, the contact metal comprising titanium and silicon;
a first contact plug in the first opening on the contact metal; and
a second contact plug in the second opening on the contact metal.

9. The integrated circuit structure of claim 8 , further comprising:
an isolation region, wherein the body protrudes through the isolation region, and wherein a portion of the gate electrode, a portion of the first dielectric spacer, and a portion of the second dielectric spacer are over the isolation region.

10. The integrated circuit structure of claim 8 , further comprising:
a gate dielectric layer, wherein the gate electrode is on the gate dielectric layer, wherein the gate dielectric layer comprises a high-k dielectric material, and wherein the gate electrode comprises a metal layer.

11. The integrated circuit structure of claim 8 , wherein the first source or drain region comprises three or more facets, and the second source or drain region comprises three or more facets.

12. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a fin comprising silicon;
a gate electrode over the fin, the gate electrode having a first side, and the gate electrode having a second side opposite the first side;
a first dielectric spacer along the first side of the gate electrode;
a first source or drain region in the fin proximate the first side of the gate electrode, a portion of the first source or drain region beneath the first dielectric spacer, wherein the first source or drain region comprises a concentration of germanium in excess of 50%, the first source or drain region comprises a boron concentration in excess of 1E20, and the first source or drain region comprises two or more facets and a top surface;
a second dielectric spacer along the second side of the gate electrode;
a second source or drain region in the fin proximate the second side of the gate electrode, a portion of the second source or drain region beneath the second dielectric spacer, wherein the second source or drain region comprises a concentration of germanium in excess of 50%, the second source or drain region comprises a boron concentration in excess of 1E20, and the second source or drain region comprises two or more facets and a top surface;
a dielectric layer over the first source or drain region and over the second source or drain region, the dielectric layer having a first opening exposing only a portion of the first source or drain region, and the dielectric layer having a second opening ex

Assignees

• Intel Corp

Inventors

• Glass Glenn A
• Murthy Anand S
• Ghani Tahir

Classifications

• H10P32/30

  Diffusion for doping of conductive or resistive layers · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10D64/0111 Primary

  to Group IV semiconductors · CPC title