Transistors with high concentration of boron doped germanium

Patent metadata

Field	Value
Publication number	US-9627384-B2
Application number	US-201414535387-A
Country	US
Kind code	B2
Filing date	Nov 7, 2014
Priority date	Dec 21, 2010
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm −3 . A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

First claim

What is claimed is:

1. A transistor device comprising:
a substrate having a channel region;
a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region and spacers are provided on sides of the gate electrode; and
source and drain regions disposed in respective cavities defined in the substrate and adjacent to the channel region, each of the source and drain regions including a tip region that extends under at least one of a corresponding one of the spacers and the gate dielectric layer, wherein the source and drain regions and corresponding tip regions comprise a boron-doped germanium layer having
a germanium concentration in excess of 50 atomic %, and
a boron concentration in excess of 1E20 cm −3 .

2. The device of claim 1 further comprising a buffer between the substrate and the boron-doped germanium layer, wherein the buffer comprises a boron-doped silicon germanium layer having:
a germanium concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 95 atomic %; and
a boron concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 1E20 cm −3 .

3. The device of claim 2 , wherein the high concentration reflects pure germanium.

4. The device of claim 1 , wherein the boron-doped germanium layer has a bi-layer construction comprising:
a boron-doped silicon germanium portion; and
a boron-doped germanium cap thereon.

5. The device of claim 4 , wherein:
the boron-doped silicon germanium portion has a germanium concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 50 atomic %; and
the boron-doped germanium cap has a germanium concentration in excess of 95 atomic %.

6. The device of claim 4 , wherein the boron-doped silicon germanium portion has a boron concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 1E20 cm −3 .

7. The device of claim 4 , wherein:
the boron-doped silicon germanium portion has a fixed germanium concentration; and
the device further comprises a buffer between the boron-doped silicon germanium portion and the boron-doped germanium cap, the buffer having
a germanium concentration that is graded from a base level concentration compatible with the boron-doped silicon germanium portion to a high concentration in excess of 50 atomic %, and
a boron concentration that is graded from a base level concentration compatible with the boron-doped silicon germanium portion to a high concentration in excess of 1E20 cm −3 .

8. The device of claim 1 , wherein the device is one of a planar or FinFET PMOS transistor.

9. A transistor device comprising:
a substrate having a channel region;
a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region and spacers are provided on sides of the gate electrode;
source and drain regions disposed in respective cavities defined in the substrate and adjacent to the channel region, each of the source and drain regions including a tip region that extends under at least one of a corresponding one of the spacers and the gate dielectric layer, wherein the source and drain regions and corresponding tip regions comprise a boron-doped germanium layer having
a germanium concentration in excess of 50 atomic %, and
a boron concentration in excess of 2E20 cm −3 ; and

metal-germanide source and drain contacts.

10. The device of claim 9 further comprising a buffer between the substrate and the boron-doped germanium layer, the buffer having:
a germanium concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 95 atomic %; and
a boron concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 2E20 cm −3 .

11. The device of claim 9 , wherein the boron-doped germanium layer has a bi-layer construction comprising:
a boron-doped silicon germanium portion; and
a boron-doped germanium cap thereon.

12. The device of claim 11 , wherein:
the boron-doped silicon germanium portion has a germanium concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 50 atomic %; and
the boron-doped germanium cap has a germanium concentration in excess of 95 atomic %.

13. The device of claim 12 , wherein the boron-doped silicon germanium portion has a boron concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 2E20 cm −3 .

14. The device of claim 11 , wherein:
the boron-doped silicon germanium portion has a fixed germanium concentration; and
the device further comprises a thin buffer between the boron-doped silicon germanium portion and the boron-doped germanium cap, the buffer having
a germanium concentration that is graded from a base level concentration compatible with the boron-doped silicon germanium portion to a high concentration in excess of 50 atomic %,
a boron concentration that is graded from a base level concentration compatible with the boron-doped silicon germanium portion to a high concentration in excess of 2E20 cm −3 , and
a thickness of less than 100 Å.

15. A method of forming a transistor device, the method comprising:
providing a substrate having a channel region;
providing a gate electrode above the channel region, wherein a gate dielectric layer is provided between the gate electrode and the channel region and spacers are provided on sides of the gate electrode; and
depositing source and drain regions in respective cavities defined in the substrate and adjacent to the channel region, each of the source and drain regions including a tip region that extends under at least one of a corresponding one of the spacers and the gate dielectric layer, wherein the source and drain regions and corresponding tip regions comprise a boron-doped germanium layer having
a germanium concentration in excess of 50 atomic %, and
a boron concentration in excess of 1E20 cm −3 .

16. The method of claim 15 further comprising:
providing a buffer between the substrate and the boron-doped germanium layer, the buffer having
a germanium concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 95 atomic %, and
a boron concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 1E20 cm −3 .

17. The method of claim 15 , wherein the boron-doped germanium layer has a bi-layer construction comprising:
a boron-doped silicon germanium portion; and
a boron-doped germanium cap thereon.

18. The method of claim 17 , wherein:
the boron-doped silicon germanium portion has a germanium concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 50 atomic %; and
the boron-doped germanium cap has a germanium concentration in excess of 95 atomic %.

19. The method of claim 17 , wherein the boron-doped silicon germanium portion has a fixed germanium concentration, the method further comprising:
providing a buffer between the boron-doped silicon germanium portion and the boron-dop

Assignees

• Intel Corp

Inventors

• Murthy Anand S
• Glass Glenn A
• Ghani Tahir
• Pillarisetty Ravi
• Mukherjee Niloy
• Kavalieros Jack T
• Kotlyar Roza
• Rachmady Willy
• Liu Mark Y

Classifications

• H10P32/30

  Diffusion for doping of conductive or resistive layers · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10D64/0111 Primary

  to Group IV semiconductors · CPC title