Column IV transistors for PMOS integration

Patent metadata

Field	Value
Publication number	US-9437691-B2
Application number	US-201113990249-A
Country	US
Kind code	B2
Filing date	Dec 20, 2011
Priority date	Dec 21, 2010
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each include a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

First claim

What is claimed is:

1. A transistor device, comprising:
a substrate having a silicon channel region;
a gate electrode above the silicon channel region; and
source and drain regions formed on or in the substrate and adjacent to the silicon channel region, wherein each of the source and drain regions:
extends above a height of the silicon channel region;
includes a tip region that extends under the gate electrode; and
has a total thickness comprising:
a p-type liner of silicon or germanium or silicon germanium; and
a p-type cap having a germanium concentration in excess of 80 atomic %, wherein the liner is less than 50% of the total thickness and lines the tip region extending under the gate electrode.

2. The device of claim 1 wherein the device is one of a planar, FinFET, or nanowire PMOS transistor.

3. The device of claim 1 further comprising metal-germanide source and drain contacts.

4. The device of claim 1 wherein the thickness ratio of liner thickness to cap thickness is 2:5, or less.

5. The device of claim 1 wherein the thickness ratio of liner thickness to cap thickness is 1:5, or less.

6. The device of claim 1 wherein each of the liners has a thickness in the range of about one monolayer to 10 nm, and each of the caps has a thickness in the range of about 50 nm to 500 nm.

7. The device of claim 1 wherein at least one of the liners and caps has at least one of a graded concentration of germanium and p-type dopant.

8. The device of claim 7 wherein at least one of the liners has a germanium concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 50 atomic %.

9. The device of claim 8 wherein the high concentration is in excess of 90 atomic %.

10. The device of claim 7 wherein at least one of the liners has a p-type dopant concentration that is graded from a base level concentration compatible with the substrate to a high concentration in excess of 1E20 cm −3 .

11. The device of claim 10 wherein the p-dopant of the one or more liners is boron.

12. The device of claim 7 wherein at least one of the caps has a germanium concentration in excess of 95 atomic %.

13. The device of claim 7 wherein at least one of the caps has a germanium concentration that is graded from a base level concentration compatible with the corresponding liner to a high concentration in excess of 80 atomic %.

14. The device of claim 7 wherein at least one of the caps has a p-type dopant concentration that is graded from a base level concentration compatible with the corresponding liner to a high concentration in excess of 1E20 cm −3 .

15. The device of claim 14 wherein the p-dopant of the one or more caps is boron.

16. The device of claim 1 wherein at least one of the caps further comprises tin.

17. The device of claim 1 wherein the caps are free of misfit dislocations, threading dislocations, and twins.

18. An electronic device comprising:
a printed circuit board having an integrated circuit including one or more transistor devices as defined in claim 1 .

19. The electronic device of claim 18 wherein the integrated circuit comprises at least one of a communication chip and a processor.

20. The electronic device of claim 18 wherein the electronic device is a computing device.

21. An integrated circuit, comprising:
the device of claim 1 , wherein the liner is less than 40% of the total thickness; and
metal-germanide source and drain contacts;
wherein at least one of the thickness ratio of liner thickness to cap thickness is 1:5 or less, and at least one of the caps further comprises tin.

22. A method for forming a transistor device, comprising:
providing a substrate having a silicon channel region;
providing a gate electrode above the silicon channel region; and
providing source and drain regions formed on or in the substrate and adjacent to the silicon channel region, wherein each of the source and drain regions:
extends above a height of the silicon channel region;
includes a tip region that extends under the gate electrode; and
has a total thickness comprising:
a p-type liner of silicon or germanium or silicon germanium; and
a p-type cap having a germanium concentration in excess of 80 atomic %, wherein the liner is less than 50% of the total thickness and lines the tip region extending under the gate electrode.

23. A transistor device, comprising:
a silicon-containing substrate having a channel region;
a gate electrode above the channel region; and
source and drain regions formed on or in the substrate and adjacent to the channel region, wherein each of the source and drain regions:
extends above a height of the channel region;
includes a tip region that extends under the gate electrode; and
has a total thickness comprising:
a p-type liner of silicon or silicon germanium; and
a p-type cap having a germanium concentration in excess of 80 atomic %, wherein the liner is less than 50% of the total thickness and lines the tip region extending under the gate electrode.

24. A transistor device, comprising:
a germanium substrate having a channel region;
a gate electrode above the channel region; and
source and drain regions formed on or in the substrate and adjacent to the channel region, wherein each of the source and drain regions:
extends above a height of the channel region;
includes a tip region that extends under the gate electrode; and
has a total thickness comprising:
a p-type liner of germanium; and
a p-type cap having a germanium concentration in excess of 80 atomic %, wherein the liner is less than 50% of the total thickness and lines the tip region extending under the gate electrode.

25. The device of claim 24 wherein each liner is included in the composition of the corresponding cap.

Assignees

• Glass Glenn A
• Murthy Anand S
• Intel Corp

Inventors

• Glass Glenn A
• Murthy Anand S

Classifications

• H10P32/30

  Diffusion for doping of conductive or resistive layers · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10D64/0111 Primary

  to Group IV semiconductors · CPC title