Memory device and memory unit

Patent metadata

Field	Value
Publication number	US-10879312-B2
Application number	US-201916536180-A
Country	US
Kind code	B2
Filing date	Aug 8, 2019
Priority date	Dec 25, 2012
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

There are provided a memory device and a memory unit that make it possible to improve retention property of a resistance value in low-current writing. The memory device of the technology includes a first electrode, a memory layer, and a second electrode in order, in which the memory layer includes an ion source layer containing one or more transition metal elements selected from group 4, group 5, and group 6 in periodic table, one or more chalcogen elements selected from tellurium (Te), sulfur (S), and selenium (Se), and one or both of boron (B) and carbon (C), and a resistance change layer having resistance that is varied by voltage application to the first electrode and the second electrode.

First claim

What is claimed is:

1. A memory device, comprising:
a first electrode, a memory layer, and a second electrode, wherein
the memory layer is between the first electrode and the second electrode, and
the second electrode comprises copper (Cu); and

a first material that covers a surface of the second electrode, wherein
the first material includes tantalum nitride (TaN), and
the memory layer includes:
an ion source layer in contact with the first electrode, wherein the ion source layer is free from copper (Cu), aluminum (Al),
silver (Ag), and zinc (Zn), and
the ion source layer contains:
 at least one transition metal element selected from at least one of group 4, group 5, or group 6 in a periodic table,
 at least one chalcogen element selected from tellurium (Te), sulfur (S), and selenium (Se), and
 at least one of boron (B) or carbon (C); and

a resistance change layer, wherein
a resistance value of the resistance change layer is variable based on application of a voltage to the first electrode and the second electrode, and
the resistance change layer includes boron oxide (BOx) and silicon oxide (SiOx).

2. The memory device according to claim 1 , wherein the resistance change layer is in contact with the second electrode.

3. The memory device according to claim 1 , wherein the resistance change layer further contains at least one of oxygen (O), nitrogen (N), boron (B), or carbon (C).

4. The memory device according to claim 1 , wherein the resistance change layer further contains an oxide, an oxynitride, and a nitride of at least one of zirconium (Zr), hafnium (Hf), aluminum (Al), or rare earth elements.

5. The memory device according to claim 1 , wherein
a change in the resistance value of the resistance change layer is based on a variation in an oxygen defect concentration in a low resistance part of the resistance change layer, and
the variation in the oxygen defect concentration in the low resistance part of the resistance change layer is based on the application of the voltage to the first electrode and the second electrode.

6. The memory device according to claim 1 , wherein the ion source layer further contains an element that forms a conduction path in the resistance change layer.

7. The memory device according to claim 1 , wherein a film thickness of the first electrode is 30 nm.

8. The memory device according to claim 1 , wherein a content of the carbon (C) in the ion source layer is 3 at % or greater and 35 at % or lower.

9. The memory device according to claim 1 , wherein the ion source layer further contains oxygen (O).

10. The memory device according to claim 1 , wherein the ion source layer further contains one of manganese (Mn), cobalt (Co), iron (Fe), nickel (Ni), platinum (Pt), or silicon (Si).

11. The memory device according to claim 1 , wherein the ion source layer further contains at least one of titanium (Ti), zirconium (Zr), or hafnium (Hf).

12. The memory device according to claim 1 , wherein the ion source layer further contains at least one of vanadium (V), niobium (Nb), or tantalum (Ta).

13. The memory device according to claim 1 , wherein the ion source layer further contains at least one of chromium (Cr), molybdenum (Mo), and tungsten (W).

14. A memory unit, comprising:
a plurality of memory devices, wherein
each memory device of the plurality of memory devices includes:
a first electrode, a memory layer, and a second electrode, wherein
the memory layer is between the first electrode and the second electrode, and
the second electrode comprises copper (Cu); and

a first material that covers a surface of the second electrode, wherein
the first material includes tantalum nitride (TaN); and

a pulse application section configured to selectively apply a pulse of one of a voltage or a current to the plurality of memory devices, wherein the memory layer includes:
an ion source layer in contact with the first electrode, wherein
the ion source layer is free from copper (Cu), aluminum (Al), silver (Ag), and zinc (Zn), and
the ion source layer contains:
at least one of boron (B) or carbon (C),
at least one transition metal element selected from at least one of group 4, group 5, or group 6 in a periodic table, and
at least one chalcogen element selected from tellurium (Te), sulfur (S), and selenium (Se); and

a resistance change layer, wherein
a resistance value of the resistance change layer is variable based on the application of the pulse, and
the resistance change layer includes boron oxide (BOx) and silicon oxide (SiOx).

Assignees

• Sony Corp

Inventors

• Sei Hiroaki
• Ohba Kazuhiro
• Nonoguchi seiji

Classifications

• H01L45/143

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L45/149

  Electricity · mapped topic

• H01L45/142

  Electricity · mapped topic

• H01L27/2463 Primary

  Electricity · mapped topic