Semiconductor device and method of manufacture

Patent metadata

Field	Value
Publication number	US-9859258-B2
Application number	US-201615157220-A
Country	US
Kind code	B2
Filing date	May 17, 2016
Priority date	May 17, 2016
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device includes a first set of through vias between and connecting a top package and a redistribution layer (RDL), the first set of through vias in physical contact with a molding compound and separated from a die. The semiconductor device also includes a first interconnect structure between and connecting the top package and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound. The first interconnect structure includes a second set of through vias and at least one integrated passive device.

First claim

What is claimed is:

1. A semiconductor device comprising:
a redistribution layer (RDL);
a die disposed on the RDL;
a first set of through vias between and connecting a top substrate and the RDL, the first set of through vias in physical contact with a molding compound and separated from the die by the molding compound; and
a first interconnect structure between and connecting the top substrate and the RDL, the first interconnect structure separated from the die and from the first set of through vias by the molding compound, the first interconnect structure comprising:
at least one passive device; and
a second set of through vias within the first interconnect structure.

2. The semiconductor device of claim 1 , wherein the at least one passive device is a trench capacitor.

3. The semiconductor device of claim 1 , wherein the passive device comprises a conductive pillar over the second set of through vias.

4. The semiconductor device of claim 3 , wherein the conductive pillar is in physical contact with the molding compound.

5. The semiconductor device of claim 1 , wherein the first interconnect structure further comprises a metallization layer, and wherein the at least one passive device is connected to the die through the metallization layer.

6. The semiconductor device of claim 1 , further comprising a second interconnect structure between and connecting the top substrate and the RDL, the second interconnect structure separated from the die, from the first interconnect structure, and from the first set of through vias by the molding compound.

7. The semiconductor device of claim 1 , wherein the first set of through vias surrounds the die and the first interconnect structure is disposed within the first set of through vias.

8. The semiconductor device of claim 1 , further comprising a top package disposed over the die and the first interconnect structure.

9. A semiconductor device comprising:
a layer between a package and a redistribution layer (RDL), the layer comprising:
a semiconductor die, wherein a first side of the semiconductor die is connected to the RDL and a second side of the semiconductor die is attached to a polymer layer;
at least one first via extending from a first side of the layer to a second side of the layer;
a first passive device structure, the first passive device structure comprising:
at least one passive device; and
at least one second via disposed within the first passive device structure

a second passive device structure, the second passive device structure comprising:
at least one passive device; and
at least one third via disposed within the second passive device structure;

a molding compound surrounding the semiconductor die, the at least one first via, the first passive device structure, and the second passive device structure, wherein the first passive device structure is separated from the at least one first via and the second passive device structure by the molding compound, wherein the at least one first via extends from a first side of the molding compound to a second side of the molding compound; and

wherein the at least one first via, the at least one second via, and the at least one third via connect the RDL and the package, wherein the at least one second via and the at least one third via are through substrate vias (TSVs).

10. The semiconductor device of claim 9 , further comprising a third passive device structure.

11. The semiconductor device of claim 9 , wherein the at least one second via has an aspect ratio from about 3:1 to about 10:1.

12. The semiconductor device of claim 9 , wherein the at least one first via has a larger width than the at least one second via.

13. The semiconductor device of claim 9 , wherein the at least one second via is connected to the package through a redistribution layer.

14. The semiconductor device of claim 9 , wherein the at least one second via is connected to the RDL through a metallization layer.

15. The semiconductor device of claim 9 , wherein the semiconductor die is connected to the at least one passive device of the first passive device structure through the RDL.

16. A semiconductor device comprising:
a set of vias disposed on and connected to a redistribution layer (RDL);
a die disposed on and connected to the RDL, wherein the die is separated from the set of vias by an encapsulant; and
a first interconnect structure disposed on and connected to the RDL, wherein the first interconnect structure is separated from the die and the set of vias by the encapsulant, wherein the encapsulant is in physical contact with the set of vias, the die, and the first interconnect structure, wherein respective top surfaces of the set of vias, the die, the encapsulant, and the first interconnect structure are level, and wherein the first interconnect structure comprises:
a substrate;
at least one through conductive element extending from one side of the substrate to a second side of the substrate; and
at least one integrated passive device.

17. The semiconductor device of claim 16 , wherein the die is connected to the at least one integrated passive device of the first interconnect device structure through the RDL.

18. The semiconductor device of claim 16 , further comprising a top package disposed over the set of vias, the die, and the first interconnect structure, wherein the top package is connected to the set of vias and the first interconnect structure.

19. The semiconductor device of claim 16 , further comprising a second interconnect structure disposed on and connected to the RDL.

20. The semiconductor device of claim 16 , wherein the at least one integrated passive device is a trench capacitor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Wei-Yu
• Yang Tien-Chung
• Su An-Jhih
• Chen Hsien-Wei

Classifications

• H10W70/6525

  for securing the interconnections to the substrate, e.g. to prevent peeling · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title