Processor load using a bit vector to calculate effective address

Patent metadata

Field	Value
Publication number	US-10877755-B2
Application number	US-201916284666-A
Country	US
Kind code	B2
Filing date	Feb 25, 2019
Priority date	Oct 18, 2016
Publication date	Dec 29, 2020
Grant date	Dec 29, 2020

Abstract

Circuitry may be configured to identify a particular element position of a bit vector stored in a register, where a value of the element occupying the particular element position matches a first predetermined value, and determine an address value dependent upon the particular element position of the bit vector and a base address. The circuitry may be further configured to load data from a memory dependent upon the address value.

First claim

What is claimed is:

1. An apparatus for performing a comparison operation with comparison data, the apparatus, comprising:
a first register configured to store a bit vector, wherein the bit vector includes a plurality of elements that occupy N ordered element positions, wherein N is a positive integer; and
circuitry configured to:
identify a particular element position of the bit vector that is storing a particular bit value;
determine an address value using the particular element position;
retrieve data from a memory circuit using the address value;
perform the comparison operation using the comparison data and the data retrieved from the memory circuit; and
update, based on a result of the comparison operation, a bit value stored in the particular element position; and

a cache memory circuit configured to store, prior to performing the comparison operation, the data retrieved from the memory circuit for subsequent use.

2. The apparatus of claim 1 , further comprising a second register configured to store a base address value, and wherein to determine the address value, the circuitry is further configured to add an address offset to the base address value, wherein the address offset is based on the particular element position.

3. The apparatus of claim 2 , further comprising a third register configured to store an offset value, and wherein the circuitry is further configured to perform a shift operation on the offset value to generate the address offset.

4. The apparatus of claim 1 , wherein the particular bit value is a logical-1.

5. The apparatus of claim 1 , wherein the comparison operation is either a greater than operation or a less than operation.

6. The apparatus of claim 1 , wherein the circuitry is further configured to repeat the comparison operation for remaining element positions of the bit vector whose value matches the particular bit value.

7. A method, comprising:
fetching an instruction by a load store unit included in a processor;
in response to determining the instruction is a bit vector instruction:
calculating an address using a location of a particular value in a bit vector associated with the bit vector instruction;
retrieving data from a memory circuit using the addres;
performing a comparison operation using the data retrieved from the memory circuit;
updating, based on a result of the comparison operation, a bit value stored in the location of the particular value in the bit vector; and
storing, prior to performing the comparison operation, the data retrieved from the memory circuit in a cache memory for subsequent use.

8. The method of claim 7 , wherein calculating the address includes adding an address offset to a base address value stored in a first register circuit, wherein the address offset is based on the location of the particular value in the bit vector.

9. The method of claim 8 , further comprising performing a shift operation on a pointer value stored in second register circuit to generate the address offset.

10. The method of claim 7 ,
wherein the bit vector includes a plurality of elements that occupy N ordered element positions, wherein N is a positive integer.

11. The method of claim 7 , wherein the particular value is a logical-1 and wherein the comparison operation includes either a greater than operation or a less than operation.

12. The method of claim 7 , repeating the comparison operation for remaining element positions of the bit vector whose value matches the particular value.

13. The method of claim 7 , further comprising, in response to calculating the address, incrementing a pointer value corresponding to the location of the particular value in the bit vector.

14. An apparatus, comprising:
a memory circuit;
a processor circuit including a load store unit configured to:
fetch an instruction from the memory circuit;
in response to a determination that the instruction is a bit vector instruction:
calculating an address using a location of a particular value in a bit vector associated with the bit vector instruction; and
retrieving data from the memory circuit using the address;
performing a comparison operation using the data retrieved from the memory circuit and comparison data; and
updating, based on a result of the comparison operation, a bit value stored in the location of the particular value in the bit vector; and

a cache memory circuit configured to store, prior to the processor circuit performing the comparison operation, the data retrieved from the memory circuit for subsequent use.

15. The apparatus of claim 14 , wherein to calculate the address, the load store unit is further configured to add an address offset to a base address value stored in a first register circuit, wherein the address offset is based on the location of the particular value in the bit vector.

16. The apparatus of claim 15 , wherein the load store unit is further configured to perform a shift operation on a pointer value stored in a second register circuit to generate the address offset.

17. The apparatus of claim 15 , wherein to calculate the address, the load store unit is further configured to retrieve the address offset from a second register circuit.

18. The apparatus of claim 14 , wherein to perform the comparison operation, the load store unit is further configured to to perform either a greater than operation or a less than operation.

19. The apparatus of claim 14 , wherein the bit vector includes a plurality of elements that occupy N ordered element positions, wherein N is a positive integer.

20. The apparatus of claim 14 , wherein the particular value is a logical-1.

Assignees

• Oracle Int Corp

Inventors

• Schlanger Erik
• Roth Charles
• Fowler Daniel

Classifications

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30018

  Bit or string instructions · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/30021 Primary

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title