Vector exception code

Patent metadata

Field	Value
Publication number	US-9715385-B2
Application number	US-201313748504-A
Country	US
Kind code	B2
Filing date	Jan 23, 2013
Priority date	Jan 23, 2013
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

Vector exception handling is facilitated. A vector instruction is executed that operates on one or more elements of a vector register. When an exception is encountered during execution of the instruction, a vector exception code is provided that indicates a position within the vector register that caused the exception. The vector exception code also includes a reason for the exception.

First claim

What is claimed is:

1. A computer program product for facilitating exception handling, the computer program product comprising:
a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
determining, by a processor, that an instruction executing within a computing environment has caused an exception, the instruction to operate on a vector register comprising a plurality of elements;
obtaining, based on the exception, a vector exception code, the vector exception code including a position within the vector register of an element of the plurality of elements of the vector register that caused the exception; and
outputting the vector exception code, including the position within the vector register of the element that caused the exception, in order to perform one or more actions based on the vector exception code.

2. The computer program product of claim 1 , wherein the position comprises an index within the vector register corresponding to the element that caused the exception.

3. The computer program product of claim 1 , wherein the position comprises a lowest indexed element in the vector register which caused the exception.

4. The computer program product of claim 1 , wherein the obtaining is based on the exception causing an interrupt.

5. The computer program product of claim 1 , wherein the vector exception code comprises a first portion to specify the position, and a second portion to specify a vector interrupt code.

6. The computer program product of claim 5 , wherein the position comprises a lowest indexed element in the vector register which caused the exception.

7. The computer program product of claim 5 , wherein the vector interrupt code comprises a value to indicate one of an invalid operation, division by zero, an overflow, an underflow or an inexact result.

8. The computer program product of claim 1 , wherein the method further comprises determining which one or more elements of the vector register caused the exception, and obtaining, based on the determining which one or more elements caused the exception, the position to be included in the vector exception code.

9. The computer program product of claim 8 , wherein the obtaining the position comprises determining the lowest indexed element of the one or more elements that caused the exception and using an index of the lowest indexed element as the position.

10. A computer system for facilitating exception handling, the computer system comprising:
a memory; and
a processor in communications with the memory, wherein the computer system is configured to perform a method, said method comprising:
determining, by a processor, that an instruction executing within a computing environment has caused an exception, the instruction to operate on a vector register comprising a plurality of elements;
obtaining, based on the exception, a vector exception code, the vector exception code including a position within the vector register of an element of the plurality of elements of the vector register that caused the exception; and
outputting the vector exception code, including the position within the vector register of the element that caused the exception, in order to perform one or more actions based on the vector exception code.

11. The computer system of claim 10 , wherein the position comprises an index within the vector register corresponding to the element which caused the exception.

12. The computer system of claim 10 , wherein the vector exception code comprises a first portion to specify the position, and a second portion to specify a vector interrupt code.

13. The computer system of claim 12 , wherein the position comprises an index within the vector register corresponding to the element which caused the exception.

14. The computer system of claim 12 , wherein the vector interrupt code comprises a value to indicate one of an invalid operation, division by zero, an overflow, an underflow or an inexact result.

15. The computer system of claim 10 , wherein the method further comprises determining which one or more elements of the vector register caused the exception, and obtaining, based on the determining which one or more elements caused the exception, the position to be included in the vector exception code, and wherein the obtaining the position comprises determining the lowest indexed element of the one or more elements that caused the exception and using an index of the lowest indexed element as the position.

16. The computer program product of claim 1 , wherein the instruction includes at least one Single Instruction, Multiple Data operation.

17. The computer program product of claim 1 , wherein the method further comprises placing the vector exception code in a data exception code field of a floating point control register.

18. The computer program product of claim 1 , wherein a size of the element is specified in a field of the instruction.

19. The computer system of claim 10 , wherein the instruction includes at least one Single Instruction, Multiple Data operation.

20. The computer system of claim 10 , wherein the method further comprises placing the vector exception code in a data exception code field of a floating point control register.

Assignees

• IBM

Inventors

• Bradbury Jonathan D
• Gschwind Michael K
• Schwarz Eric M
• Slegel Timothy J

Classifications

• G06F9/30098

  Register arrangements · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/3005

  to perform operations for flow control · CPC title

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30038

  using a mask · CPC title