Semiconductor package with leadframe interconnection structure

Patent metadata

Field	Value
Publication number	US-10872848-B2
Application number	US-201816170692-A
Country	US
Kind code	B2
Filing date	Oct 25, 2018
Priority date	Oct 25, 2018
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

An embodiment of a semiconductor package includes a leadframe and a mold compound partly encasing the leadframe so that leads protrude from the mold compound and at least two die pads have a surface at a first side of the leadframe which is not covered by the mold compound. A laser module is attached to the surface of the at least two die pads which is not covered by the mold compound. A driver die is attached to the leadframe at a second side of the leadframe opposite the first side so that the laser module and the driver die are disposed in a stacked arrangement, the driver die configured to control the laser module. The driver die is in direct electrical communication with the laser module only through the leadframe and any interconnects which attach the laser module and driver die to the leadframe.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a leadframe comprising leads and a plurality of die pads;
a mold compound partly encasing the leadframe so that the leads protrude from the mold compound and at least two of the plurality of die pads have a surface at a first side of the leadframe which is not covered by the mold compound;
a laser module attached to the surface of the at least two die pads which is not covered by the mold compound, the laser module configured to emit laser light outward from the semiconductor package; and
a driver die attached to the leadframe at a second side of the leadframe opposite the first side so that the laser module and the driver die are disposed in a stacked arrangement, the driver die configured to control the laser module,
wherein the driver die is in direct electrical communication with the laser module only through the leadframe and any interconnects which attach the laser module and the driver die to the leadframe.

2. The semiconductor package of claim 1 , wherein the leads extend along a first plane within the mold compound, and wherein the at least two die pads extend along a second plane within the mold compound different than the first plane so that a step is provided between the at least two die pads and the leads within the mold compound.

3. The semiconductor package of claim 1 , wherein the leads and the at least two die pads extend along a same first plane within the mold compound.

4. The semiconductor package of claim 3 , wherein the mold compound has an opening which extends to the surface of the at least two die pads, and wherein the laser module is disposed in the opening.

5. The semiconductor package of claim 4 , further comprising a transparent epoxy covering the laser module and filling the opening in the mold compound.

6. The semiconductor package of claim 4 , wherein a thickness of the laser module is less than a height of the opening in the mold compound, and wherein the thickness of the laser module and the height of the opening are measured in a direction perpendicular to the first side of the leadframe.

7. The semiconductor package of claim 1 , further comprising one or more capacitors attached to the first side of the leadframe or to a second side of the leadframe opposite the first side.

8. The semiconductor package of claim 7 , wherein the one or more capacitors are encased in the mold compound.

9. The semiconductor package of claim 7 , wherein the first side of the leadframe is not covered by the mold compound so that the one or more capacitors are not encased in the mold compound.

10. A method of manufacturing a semiconductor package, the method comprising:
providing a leadframe comprising leads and a plurality of die pads;
partly encasing the leadframe in a mold compound so that the leads protrude from the mold compound and at least two of the plurality of die pads have a surface at a first side of the leadframe which is not covered by the mold compound;
attaching a laser module to the surface of the at least two die pads which is not covered by the mold compound, the laser module configured to emit laser light outward from the semiconductor package; and
attaching a driver die to the leadframe at a second side of the leadframe opposite the first side so that the laser module and the driver die are disposed in a stacked arrangement, the driver die configured to control the laser module,
wherein the driver die is in direct electrical communication with the laser module only through the leadframe and any interconnects which attach the laser module and the driver die to the leadframe.

11. The method of claim 10 , wherein the leads extend along a first plane within the mold compound, wherein the at least two die pads extend along a second plane within the mold compound different than the first plane so that a step is provided between the at least two die pads and the leads within the mold compound, and wherein the driver die is attached to the leadframe in a flip-chip configuration.

12. The method of claim 10 , wherein the leads and the at least two die pads extend along a same first plane within the mold compound, wherein the driver die is attached to the leadframe in a flip-chip configuration, and wherein the surface at the first side of the leadframe which is not covered by the mold compound via an over-molded film-assist molding process.

13. The method of claim 12 , wherein an opening is formed in the mold compound during the over-molded film-assist molding process, the opening extending to the surface of the at least two die pads and sized to receive the laser module.

14. The method of claim 13 , further comprising:
covering the laser module and filling the opening in the mold compound with a transparent epoxy.

15. The method of claim 10 , further comprising:
attaching one or more capacitors to the first side of the leadframe or to a second side of the leadframe opposite the first side.

Assignees

• Infineon Technologies Ag

Inventors

• Yong Woon Yik
• Kucher Andreas
• Lee Chia-Yen
• Wan Shao Ping

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/012

  of bump connectors, dummy bumps or thermal bumps · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title