Gate driving circuit, shift register and driving control method thereof

Patent metadata

Field	Value
Publication number	US-10872549-B2
Application number	US-201816332944-A
Country	US
Kind code	B2
Filing date	Aug 10, 2018
Priority date	Oct 16, 2017
Publication date	Dec 22, 2020
Grant date	Dec 22, 2020

Abstract

The present disclosure provides a gate driving circuit, a shift register, and a driving control method thereof. The shift register includes: a gate signal generation circuit configured to generate a first gate signal for gating transistors, wherein the gating transistors comprise a first gating transistor and a second gating transistor coupled in series; a gate signal output control circuit configured to receive a first level signal, and output a first gate signal from the gate signal generation circuit to the first gating transistor and the second gating transistor under control of the first level signal; and a control circuit configured to receive a second level signal, a first control signal, and a second control signal, and output the first control signal to the first gating transistor and output the second control signal to the second gating transistor under control of the second level signal.

First claim

We claim:

1. A shift register, comprising:
a gate signal generation circuit configured to generate a first gate signal for gating transistors, wherein the gating transistors comprise a first gating transistor and a second gating transistor coupled in series;
a gate signal output control circuit electrically coupled to the gate signal generation circuit and the gating transistors, and configured to receive a first level signal and output the first gate signal to the first gating transistor and the second gating transistor under control of the first level signal; and
a control circuit configured to receive a second level signal, a first control signal, and a second control signal, and configured to output the first control signal to the first gating transistor and output the second control signal to the second gating transistor under control of the second level signal;
wherein the gate signal generation circuit comprises:
an input sub-circuit configured to receive an input signal and a reset signal, control a potential at a pull-up node under control of the input signal, and pull down the potential at the pull-up node under control of the reset signal;
an output sub-circuit configured to receive a clock signal, and output the clock signal as the first gate signal under control of the potential at the pull-up node;
a first pull-up sub-circuit configured to receive a third control signal, and control as potential at a pull-down node under control of the third control signal;
a first pull-down sub-circuit configured to pull-down the potential at the pull-down node under control of the potential at the pull-up node, and pull down the potential at the pull-up node under control of the potential at the pull-down node; and
a second pull-down sub-circuit electrically coupled to the gating transistors and the pull-down node, and configured to pull down a voltage output to the gate of the first gating transistor and the gate of the second gating transistor under control of the potential at the pull-down node.

2. The shift register according to claim 1 , wherein the gate signal output control circuit comprises a first transistor and a second transistor,
wherein a control electrode of the first transistor and a control electrode of the second transistor are coupled to receive the first level signal, a first electrode of the first transistor and a first electrode of the second transistor are electrically coupled to the gate signal generation circuit, and a second electrode of the first transistor is electrically coupled to the gate of the first gating transistor; and
a second electrode of the second transistor is electrically coupled to the control circuit.

3. The shift register according to claim 1 , wherein the control circuit comprises a third transistor and a fourth transistor,
wherein a control electrode of the third transistor and a control electrode of the fourth transistor are coupled to receive the second level signal, a first electrode of the third transistor is coupled to receive the first control signal, and a second electrode of the third transistor is electrically coupled to the gate of the first gating transistor; and
a first electrode of the fourth transistor is coupled to receive the second control signal, and a second electrode of the fourth transistor is electrically coupled to the gate of the second gating transistor.

4. The shift register according to claim 1 , wherein the input sub-circuit comprises:
a fifth transistor having a control electrode coupled to receive the input signal, and a first electrode coupled to receive the input signal or a forward scanning signal; and
a sixth transistor having a control electrode coupled to receive the reset signal, a first electrode coupled to receive the reset signal or a reverse scanning signal, and a second electrode electrically coupled to a second electrode of the fifth transistor and the pull-up node.

5. The shift register according to claim 1 , wherein the output sub-circuit comprises:
a first capacitor having a first terminal electrically coupled to the pull-up node, and a second terminal electrically coupled to the gate signal output control circuit; and
a seventh transistor having a control electrode electrically coupled to the pull-up node, a first electrode coupled to receive the clock signal, and a second electrode electrically coupled to the second terminal of the first capacitor.

6. The shift register according to claim 1 , wherein the first pull-up sub-circuit comprises:
an eighth transistor having a control electrode and a first electrode coupled to receive the third control signal; and
a ninth transistor having a control electrode electrically coupled to a second electrode of the eighth transistor, a first electrode coupled to receive the third control signal, and a second electrode electrically coupled to the pull-down node.

7. The shift register according to claim 6 , wherein the first pull-down sub-circuit comprises:
a tenth transistor having a control electrode electrically coupled to the pull-down node, a first electrode electrically coupled to the pull-up node, and a second electrode electrically coupled to a low level voltage line;
an eleventh transistor having a control electrode electrically coupled to the pull-up node, a first electrode electrically coupled to the second electrode of the eighth transistor, and a second electrode electrically coupled to the low level voltage line; and
a twelfth transistor having a control electrode electrically coupled to the pull-up node, a first electrode electrically coupled to the pull-down node, and a second electrode electrically coupled to the low level voltage line.

8. The shift register according to claim 1 , wherein the second pull-down sub-circuit comprises a thirteenth transistor and a fourteenth transistor,
wherein a control electrode of the thirteenth transistor and a control electrode of the fourteenth transistor are electrically coupled to the pull-down node, a first electrode of the thirteenth transistor is electrically coupled to a low level voltage line, and a second electrode electrically coupled to the gate signal output control circuit; and
the fourteenth transistor has a first electrode electrically coupled to the low level voltage line, and a second electrode electrically coupled to the gate signal output control circuit.

9. A gate driving circuit, comprising the shift register according to claim 1 .

10. A driving control method for the shift register according to claim 1 , comprising:
applying, in a first phase, a first gate signal to the first gating transistor and the second gating transistor to turn on the first gating transistor and the second gating transistor at the same time; and
applying, in a second phase, a first control signal to the gate of the first gating transistor and applying a second control signal to the gate of the second gating transistor, to turn on the first gating transistor and the second gating transistor alternatively, wherein the first control signal and the second control signal are at an active level alternatively.

11. The driving control method according to claim 10 , wherein the second level signal is opposite in phase to the first level signal.

12. The driving control method according to claim 11 , wherein
in the first phase, the first level signal and the second level signal are both direct current signals; and
in the second phase, the first level signal and the second level signal are both alternating current signals.

13. The driving control method according to claim 12 , wherein
in the first phase, the first level signal is at a high level; and
in the sec

Assignees

• Beijing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Mi Lei
• Xue Yanna
• Bao Zhiying
• Zhang Yong
• Bai Lu
• Wang Jingpeng
• Hua Gang
• Fang Haobo
• Yuan Lingxiang

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2320/0214

  with crosstalk due to leakage current of pixel switch in active matrix panels · CPC title