Gate driving unit, gate driving circuit, and display device

Patent metadata

Field	Value
Publication number	US-2016012764-A1
Application number	US-201414422219-A
Country	US
Kind code	A1
Filing date	Jun 30, 2014
Priority date	Sep 6, 2013
Publication date	Jan 14, 2016
Grant date	—

Abstract

A gate driving unit includes an input circuit, a pull-up circuit, a reset circuit, and an output circuit. The pull-up driving signals received by the input circuit include the gate driving signals for pixel units of row n−2 and row n+4. The reset driving signals received by the reset circuit include the gate driving signals for pixel units of row n+2 and row n+8. The gate driving signals output from the output circuit include the gate driving signals for pixel units of row n and row n+6. Where, n is a positive integer and nε[3,∞). The gate driving unit can output gate driving signals of two rows of pixel units and thus has a high service efficiency. An area occupied by a gate driving circuit made of the gate driving units is reduced, and a driving efficiency of the gate driving circuit is increased.

First claim

1 . A gate driving unit including an input circuit, a pull-up circuit, a reset circuit, and an output circuit, the input circuit being connected to both the pull-up circuit and the reset circuit, the pull-up circuit and the reset circuit being connected to the output circuit, respectively, wherein
the input circuit is used for receiving a pull-up driving signal and inputting the pull-up driving signal to the pull-up circuit; the pull-up circuit is used for receiving the pull-up driving signal and outputting a high level signal to an input terminal of the output circuit; the reset circuit is used for receiving a reset driving signal and resetting the high level signal at the input terminal of the output circuit to a low level signal; and the output circuit is used for receiving an output signal from the pull-up circuit and an output signal from the reset circuit, and outputting a gate driving signal under control of a clock signal; wherein, the pull-up driving signals received by the input circuit include the gate driving signals for pixel units of row n−2 and row n+4, the reset driving signals received by the reset circuit include the gate driving signals for pixel units of row n+2 and row n+8, and the gate driving signals output from the output circuit include the gate driving signals for pixel units of row n and row n+6, where n is a positive integer and nε[3,∞).

2 . The gate driving unit according to claim 1 , wherein, the input circuit includes a first transistor, a second transistor, and a fifth transistor, gates of the first transistor and the second transistor are respectively connected to respective sources thereof, drains of the first transistor and the second transistor are connected to both a gate and a drain of the fifth transistor, a source of the fifth transistor is connected to both the pull-up circuit and the reset circuit, the gate driving signal of the pixel units of the row n−2 is input to the gate of the first transistor, and the gate driving signal of the pixel units of the row n+4 is input to the gate of the second transistor;
the pull-up circuit includes a sixth transistor and a capacitor connected between a gate and a source of the sixth transistor, the gate of the sixth transistor is further connected to the source of the fifth transistor in the input circuit, a drain of the sixth transistor is connected to a high potential terminal, and the source of the sixth transistor is further connected to the input terminal of the output circuit;
the reset circuit includes a third transistor, a fourth transistor, a seventh transistor, and an eighth transistor, gates of the third transistor and the fourth transistor are respectively connected to respective sources thereof, drains of the third transistor and the fourth transistor are connected to gates of both the seventh transistor and the eighth transistor, the gate of the seventh transistor is connected to the gate of the eighth transistor, a source of the seventh transistor is connected to the source of the fifth transistor in the input circuit, a source of the eighth transistor is connected to the source of the sixth transistor in the pull-up circuit, drains of the seventh transistor and the eighth transistor are connected to a low potential terminal, the gate driving signal of the pixel units of the row n+2 is input to the gate of the third transistor, and the gate driving signal of the pixel units of the row n+8 is input to the gate of the fourth transistor; and
the output circuit includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor, a gate of the eleventh transistor is connected to a first clock signal or a second clock signal, a gate of the twelfth transistor is connected to a third clock signal or a fourth clock signal, sources of the eleventh transistor and the twelfth transistor are connected to the source of the sixth transistor in the pull-up circuit, gates of the ninth transistor and the tenth transistor are connected to the gate of the seventh transistor in the reset circuit, a drain of the eleventh transistor is connected to a source of the ninth transistor and outputs the gate driving signal of the pixel units of the row n, a drain of the twelfth transistor is connected to a source of the tenth transistor and outputs the gate driving signal of the pixel units of the row n+6, and drains of the ninth transistor and the tenth transistor are connected to the low potential terminal.

3 . The gate driving unit according to claim 2 , wherein, the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal have a same pulse width and a duty ratio of ½, the first clock signal is ½ cycle ahead of the third clock signal, and the second clock signal is ½ cycle ahead of the fourth clock signal.

4 . The gate driving unit according to claim 3 , wherein, a gate driving signal of pixel units of row 1 or row 2 received by the input circuit is a ½ frame start signal.

5 . The gate driving unit according to claim 4 , wherein, the gate driving signals of pixel units of two adjacent odd-numbered rows or two adjacent even-numbered rows have an interval of ½ cycle therebetween.

6 . The gate driving unit according to claim 5 , wherein, the gate driving unit causes the pull-up circuit to be precharged through inputting the gate driving signals of pixel units of the row n−2 and the row n+4 by the input circuit;
the pull-up circuit is capable of outputting a high level signal after the precharge is finished, and under control of the first clock signal to the fourth clock signal, the high level signal causes the output circuit to output the gate driving signals of pixel units of the row n and the row n+6; and
the gate driving unit resets the output gate driving signals of pixel units of the row n and the row n+6 from a high level signal to a low level signal through inputting the gate driving signals of pixel units of the row n+2 and the row n+8 by the reset circuit.

7 - 10 . (canceled)

11 . A gate driving circuit including a plurality of gate driving units which are cascaded sequentially, each of the plurality of gate driving units including an input circuit, a pull-up circuit, a reset circuit, and an output circuit, the input circuit being connected to both the pull-up circuit and the reset circuit, the pull-up circuit and the reset circuit being connected to the output circuit, respectively, wherein
the input circuit is used for receiving a pull-up driving signal and inputting the pull-up driving signal to the pull-up circuit; the pull-up circuit is used for receiving the pull-up driving signal and outputting a high level signal to an input terminal of the output circuit;
the reset circuit is used for receiving a reset driving signal and resetting the high level signal at the input terminal of the output circuit to a low level signal; and
the output circuit is used for receiving an output signal from the pull-up circuit and an output signal from the reset circuit, and outputting a gate driving signal under control of a clock signal;
wherein, the pull-up driving signals received by the input circuit include the gate driving signals for pixel units of row n−2 and row n+4, the reset driving signals received by the reset circuit include the gate driving signals for pixel units of row n+2 and row n+8, and the gate driving signals output from the output circuit include the gate driving signals for pixel units of row n and row n+6, where n is a positive integer and nε[3,∞).

12 . The gate driving circuit according to claim 7 , wherein, the input circuit includes a first transistor, a second transistor, and a fifth transistor, gates of the first transistor and the second transistor are respectively connec

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Xu Xiangyang

Classifications

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title