Method of fabricating semiconductor package

Patent metadata

Field	Value
Publication number	US-10868073-B2
Application number	US-201816177780-A
Country	US
Kind code	B2
Filing date	Nov 1, 2018
Priority date	Aug 4, 2016
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A semiconductor package including a substrate, a memory chip on the substrate, a mold layer on the substrate to cover a side surface of the memory chip, an image sensor chip on the memory chip and the mold layer, and a connection terminal between and electrically connecting the memory chip to the image sensor chip may be provided.

First claim

What is claimed is:

1. A method of fabricating a semiconductor package, comprising:
preparing an image sensor chip having a first surface and a second surface, the first surface and the second surface being opposite to each other, the image sensor chip including pixel regions positioned on the second surface of the image sensor chip;
mounting a memory chip on the first surface of the image sensor chip such that the memory chip is electrically connected to the image sensor chip through a connection terminal formed between the first surface of the image sensor chip and a third surface of the memory chip that faces the first surface of the image sensor chip; and
forming a mold layer on the first surface of the image sensor chip to cover a first side surface of the memory chip to form a chip stack, and to not cover a fourth surface of the memory chip, the fourth surface being opposite to the third surface,
wherein the mold layer has a thermal conductivity that is lower than that of a substrate on which the chip stack provided, and
an outer side surface of the mold layer is aligned with a second side surface of the image sensor chip.

2. The method of claim 1 , further comprising:
preparing the substrate;
providing the chip stack on the substrate such that the fourth surface of the memory chip faces the substrate; and
forming a bonding wire to electrically connect the image sensor chip to the substrate.

3. The method of claim 1 , wherein the image sensor chip has a width that is larger than that of the memory chip and is substantially same as that of the mold layer.

4. The method of claim 1 , further comprising:
forming a re-distribution pattern on the first surface of the image sensor chip to electrically connect a circuit layer of the image sensor chip to the connection terminal.

5. The method of claim 1 , further comprising:
forming a dummy terminal between the memory chip and the image sensor chip such that the dummy terminal overlaps the pixel regions, when viewed in a plan view.

6. The method of claim 1 , wherein the memory chip has the third surface facing the image sensor chip and the fourth surface, and
the fourth surface of the memory chip is exposed by the mold layer.

7. The method of claim 1 , wherein the forming a mold layer includes forming the mold layer such that an inner side surface of the mold layer is in contact with the first side surface of the memory chip.

8. The method of claim 1 , wherein the forming a mold layer includes forming the mold layer such that the mold layer is on the third surface of the memory chip.

9. The method of claim 4 , wherein the forming a re-distribution pattern includes,
forming one or more insulating layers,
forming one or more conductive layers between the one or more insulating layers, and
forming one or more conductive vias penetrating at least one of the one or more insulating layers and to be coupled to a corresponding one of the one or more conductive layers.

10. The method of claim 1 , further comprising:
forming a first pad on the first surface of the image sensor chip;
forming a re-distribution pattern between the image sensor chip and the memory chip to cover the first pad; and
forming a second pad on a fifth surface of the re-distribution pattern to face and couple with the connection terminal and to be electrically connected to the first pad through the re-distribution pattern, the fifth surface of the re-distribution pattern being a surface facing the memory chip.

11. The method of claim 10 , wherein the forming a second pad forms the second pad laterally outside the memory chip.

12. The method of claim 10 , wherein the forming a first pad and the forming a second pad form the first and second pads such that the first pad is not aligned to the second pad in a direction perpendicular to the first surface.

13. The method of claim 4 , further comprising:
forming a dummy terminal between the memory chip and the image sensor chip and on the re-distribution pattern such that the dummy terminal overlaps the pixel regions, when viewed in a plan view.

14. The method of claim 13 , wherein the dummy terminal includes a conductive material, and is electrically disconnected from integrated devices in the memory chip and the re-distribution pattern.

15. The method of claim 13 , wherein the forming a dummy terminal includes forming the connection terminal and the dummy terminal simultaneously and to be separated from each other.

16. The method of claim 5 , wherein the dummy terminal includes a thermally conductive material and provides a thermal connection between the memory chip and the image sensor chip.

17. The method of claim 16 , further comprising:
forming a redistribution layer, which includes insulating layers and a re-distribution pattern, on the first surface of the image sensor chip such that the re-distribution pattern is provided between and penetrating through the insulating layers and is electrically connected to a circuit layer of the image sensor chip and the connection terminal.

18. The method of claim 17 , further comprising:
forming a metal pattern penetrating the insulating layers to be separated from the re-distribution pattern, to physically contact the image sensor chip, and to be thermally coupled with the dummy terminal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Un-Byoung
• Kong Yungcheol
• Jun Hyunsu
• Choi Kyoungsei

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W70/652

  Cross-sectional shapes · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/075

  of bond wires · CPC title