Semiconductor memory device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-2016268282-A1
Application number	US-201514751627-A
Country	US
Kind code	A1
Filing date	Jun 26, 2015
Priority date	Mar 13, 2015
Publication date	Sep 15, 2016
Grant date	—

Abstract

According to one embodiment, a semiconductor memory device includes a substrate; a conductive layer provided on the substrate; a stacked body provided on the conductive layer and including a plurality of electrode layers stacked to be separated from each other; a semiconductor pillar portion provided in the stacked body and extending in a stacking direction of the stacked body; an interconnect portion provided in the stacked body, extending in the stacking direction and a first direction crossing the stacking direction, and including a lower surface; a semiconductor portion provided in the conductive layer via an insulating film relative to the conductive layer, provided integrally with the semiconductor pillar portion; and an insulating portion. The semiconductor portion includes: a first portion; a second portion; and a third portion. The insulating portion is provided between the first portion and the second portion.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a substrate; a conductive layer provided on the substrate; a stacked body provided on the conductive layer and including a plurality of electrode layers separately stacked each other; a semiconductor pillar portion provided in the stacked body and extending in a stacking direction of the stacked body; an interconnect portion provided in the stacked body, extending in the stacking direction and a first direction crossing the stacking direction, and including a lower surface; a semiconductor portion provided relative to the conductive layer via an insulating film in the conductive layer, provided integrally with the semiconductor pillar portion, and extending in the first direction and a second direction crossing the stacking direction and the first direction, the semiconductor portion includes:
a first portion provided relative to the stacked body via the conductive layer and the insulating film;
a second portion provided between the first portion and the substrate and separated from the first portion in the stacking direction; and
a third portion having a maximum thickness being thicker than a maximum thickness of the first portion and ticker than a maximum thickness of the second portion in the stacking direction, the third portion being in contact with the lower surface; and
an insulating portion provided between the first portion and the second portion.

2 . The device according to claim 1 , wherein the insulating portion is separated in the second direction via the third portion.

3 . The device according to claim 1 , wherein the insulating portion is separated from the lower surface of the interconnect portion.

4 . The device according to claim 1 , wherein the insulating film is separated in the second direction via the interconnect portion.

5 . The device according to claim 1 , wherein, in the second direction, a maximum length of the interconnect portion is larger than a maximum length of a separated portion of the insulating film separated via the interconnect portion.

6 . The device according to claim 1 , wherein, in the stacking direction, a maximum thickness of a sum of a thickness of the first portion, a thickness of the second portion and a thickness of the insulating portion is thicker than the maximum thickness of the third portion.

7 . The device according to claim 1 , wherein the insulating portion is separated from the insulating film.

8 . The device according to claim 1 , wherein the first portion and the second portion are provided continuously in the second direction via the third portion.

9 . The device according to claim 1 , wherein
the semiconductor portion includes an impurity layer in contact with the lower surface, and the interconnect portion is electrically connected to the semiconductor pillar via the impurity layer.

10 . The device according to claim 9 , wherein an impurity concentration of the impurity layer is higher than an impurity concentration of the semiconductor pillar portion.

11 . A semiconductor memory device comprising:
a substrate; a conductive layer provided on the substrate; a stacked body provided on the conductive layer and including a plurality of electrode layers separately stacked each other; a semiconductor pillar portion provided in the stacked body and extending in a stacking direction of the stacked body; an interconnect portion provided in the stacked body, extending in the stacking direction and a first direction crossing the stacking direction, and including a lower surface; a semiconductor portion provided relative to the conductive layer via an insulating film in the conductive layer, provided integrally with the semiconductor pillar portion, and being in contact with the lower surface; and an insulating portion provided inside the semiconductor portion, and separated in the stacking direction and a second direction crossing the first direction via the semiconductor portion.

12 . The device according to claim 11 , wherein the semiconductor portion is provided between the interconnect portion and the insulating portion.

13 . The device according to claim 11 , wherein the insulating film is separated in the second direction via the interconnect portion.

14 . The device according to claim 11 , wherein a maximum thickness, in the stacking direction, of a portion of the semiconductor portion in contact with the lower surface is thinner than a maximum thickness, in the stacking direction, of the semiconductor portion including the insulating portion.

15 . The device according to claim 11 , wherein, in the stacking direction, a maximum distance between the lower surface and the insulating film is larger than a maximum distance between the insulating portion and the insulating film.

16 . The device according to claim 11 , wherein the insulating portion is separated from the insulating film.

17 . The device according to claim 11 , wherein the insulating portion includes an air gap.

18 . The device according to claim 11 , wherein
the semiconductor portion includes an impurity layer in contact with the lower surface, and the interconnect portion is electrically connected to the semiconductor pillar via the impurity layer.

19 . A method for manufacturing a semiconductor memory device, comprising:
forming a sacrifice layer on a substrate; forming an opening portion, in the sacrifice layer, extending in a first direction parallel to a major surface of the substrate; forming a conductive layer on the substrate, on the sacrifice layer and in the opening portion; forming a stacked body, on the conductive layer, including a plurality of electrode layers stacked to be separated from each other; forming a hole piercing the stacked body and the conductive layer in a stacking direction of the stacked body and reaching the sacrifice layer; forming a cavity including a protrusion of the conductive layer formed in the opening portion by removing the sacrifice layer through the hole; forming a film including a charge storage film on an inner wall of the hole and an inner wall of the cavity; separating the cavity in a second direction crossing the first direction and the stacking direction via the protrusion by forming a semiconductor portion inside the film including the charge storage film; forming a slit piercing the stacked body and the protrusion, reaching the semiconductor portion and extending in the first direction; and forming a conductive film in contact with the semiconductor portion in the slit.

20 . The method according to claim 19 , further comprising forming an insulating portion inside the semiconductor portion, the insulating portion separated in the second direction via the semiconductor portion.

Assignees

• Toshiba Kk

Inventors

• Ishibashi Shota

Classifications

• H10D62/115 Primary

  Dielectric isolations, e.g. air gaps · CPC title

• H01L27/11568 Primary

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title