Memory modules and methods of operating memory systems including the same

Patent metadata

Field	Value
Publication number	US-10867690-B2
Application number	US-201916392849-A
Country	US
Kind code	B2
Filing date	Apr 24, 2019
Priority date	Oct 24, 2018
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A memory module includes a first channel of first data memories and a first error correction code (ECC) memory, and a second channel of second data memories and a second ECC memory. Each first data memory transmits a corresponding first data set of first data sets with a memory controller. Each first data set corresponds to a burst length. Each second data memory transmits a corresponding second data set of the second data sets with the memory controller. Each second data set corresponds to the burst length. The first ECC memory stores first sub parity data for detecting at least one error in all of the first data sets stored in the first data memories. The second ECC memory stores second sub parity data for detecting at least one error in all of the second data sets stored in the second data memories.

First claim

What is claimed is:

1. A memory module comprising:
a plurality of first data memories and a first error correction code (ECC) memory that constitute a first channel; and
a plurality of second data memories and a second ECC memory that constitute a second channel,
wherein each of the plurality of first data memories is configured to transmit a corresponding first data set of a plurality of first data sets with a memory controller, each of the plurality of first data sets corresponding to a burst length,
each of the plurality of second data memories is configured to transmit a corresponding second data set of a plurality of second data sets with the memory controller, each of the plurality of second data sets corresponding to the burst length,
the first ECC memory is configured to store first sub parity data for detecting at least one error in all of the plurality of first data sets stored in the plurality of first data memories, and
the second ECC memory is configured to store second sub parity data for detecting at least one error in all of the plurality of second data sets stored in the plurality of second data memories,
wherein:
the first ECC memory includes a first parity region and a second parity region;
the first parity region stores the first sub parity data; and
the second parity region stores first internal parity bits generated based on the first sub parity data.

2. The memory module of claim 1 , wherein:
each of the plurality of first data memories has a 4-bit data input/output (I/O) width;
each of the plurality of second data memories has a 4-bit data IO width; and
each of the first ECC memory and the second ECC memory stores has a 4-bit data I/O width.

3. The memory module of claim 2 ,
wherein each of the first channel and the second channel has a 36-bit data input/output width.

4. The memory module of claim 1 , wherein:
each of the plurality of first data memories includes a memory cell array that having a first memory region and a second memory region;
the first memory region of each of the plurality of first data memories stores a corresponding first data set of the plurality of first data sets and the second memory region stores first parity bits generated from an ECC encoding operation performed on the corresponding first data set; and
the first parity bits are part of the first sub parity data.

5. The memory module of claim 4 ,
wherein each of the plurality of first data memories includes an ECC engine including:
an ECC encoder configured to perform the ECC encoding operation on the corresponding first data set of the plurality of first data sets to generate the first parity bits; and
an ECC decoder configured to perform an ECC decoding operation on a corresponding first data set of the plurality of first data sets read from the first memory region to correct an error detected from the corresponding first data set of the plurality of first data sets which are read from the first memory region.

6. The memory module of claim 1 ,
wherein the first ECC memory further includes an ECC engine including:
an ECC encoder configured to perform an ECC encoding operation on the first sub parity data to generate the first internal parity bits; and
an ECC decoder configured to perform an ECC decoding operation on the first sub parity data read from the first parity region to correct an error detected in the first sub parity data.

7. The memory module of claim 1 , wherein:
the second ECC memory includes a third parity region and a fourth parity region;
the third parity region stores the second sub parity data; and
the fourth parity region stores second internal parity bits generated based on the second sub parity data.

8. The memory module of claim 7 ,
wherein the second ECC memory further includes an ECC engine including:
an ECC encoder configured to perform an ECC encoding operation on the second sub parity data to generate the second internal parity bits; and
an ECC decoder configured to perform an ECC decoding operation on the second sub parity data read from the third parity region to correct an error detected in the second sub parity data.

9. The memory module of claim 1 , wherein:
a first error of at least one first data memory of the plurality of first data memories is detected and corrected based on the first sub parity data stored in the first ECC memory; and
a second error of at least one second data memory of the plurality of second data memories is detected and corrected based on the second sub parity data stored in the second ECC memory.

10. A memory module comprising:
a first channel including a plurality of first data memories;
a second channel including a plurality of second data memories; and
an error correction code (ECC) memory,
wherein the plurality of first data memories and the plurality of second data memories store a plurality of first data sets and a plurality of second data sets respectively,
each of the plurality of first data sets corresponds to a burst length,
each of the plurality of second data sets corresponds to the burst length, and
the ECC memory is configured to store parity data for detecting at least one error in at least one of a first sub user data set corresponding to all of the plurality of first data sets and a second sub user data set corresponding to all of the plurality of second data sets,
wherein:
the ECC memory includes a first parity region and a second parity region,
the first parity region stores at least one of first sub parity data associated with the first sub user data set and second sub parity data associated with the second sub user data set, and
the second parity region stores at least one of the first sub parity data and the second sub parity data.

11. The memory module of claim 10 , wherein:
each of the plurality of first data memories has an 8-bit data input/output (I/O) width,
each of the plurality of second data memories has an 8-bit data I/O width; and
the ECC memory has an 8-bit data IO width.

12. The memory module of claim 10 , further comprising a buffer device,
wherein the buffer device is configured to redistribute a command and an address received from an external memory controller to each of the plurality of first data memories, each of the plurality of second data memories and the ECC memory, and
the buffer device is configured to apply a pseudo channel selection signal to the ECC memory to activate at least one of the first parity region and the second parity region.

13. The memory module of claim 12 , wherein:
the first parity region, if activated by the pseudo channel selection signal, stores the first sub parity data during operation of the first channel;
the second parity region, if activated by the pseudo channel selection signal, stores the second sub parity data during operation of the second channel;
the first channel further includes the first parity region; and
the second channel further includes the second parity region.

14. The memory module of claim 12 , wherein:
the first parity region and the second parity region, if activated by the pseudo channel selection signal, store the first sub parity data during operation of the first channel;
the first parity region and the second parity region, if activated by the pseudo channel selection signal, store the second sub parity data during operation of the second channel;
each of the first channel and the second channel further includes the first parity region and the second parity region; and
the first parity region and the second parity region are shared by the first channel and the second channel.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyun-Joong
• Kim Duk-Sung
• Lee Yoo-Jung
• Choi Jang-Seok

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/783

  with refresh of replacement cells, e.g. in DRAMs · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title