Timing control for input receiver

Patent metadata

Field	Value
Publication number	US-9984740-B1
Application number	US-201715464907-A
Country	US
Kind code	B1
Filing date	Mar 21, 2017
Priority date	Mar 21, 2017
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes a signal receiver that receives information signal; a control circuit that provides a plurality of control signals; and a signal receiver replica circuit that receives a first reference signal. The signal receiver replica circuit includes a plurality of receivers. Each receiver of the plurality of receivers receives the first reference signal and a corresponding control signal of the plurality of control signals, and further provides an output signal.

First claim

What is claimed is:

1. An apparatus comprising:
a first receiver configured to receive a first input signal, a first timing signal and a first reference voltage and further configured to detect a logic level of the first input signal responsive to the first timing signal and the first reference voltage;
a second receiver configured to receive a second input signal, a second timing signal and a second reference voltage, and further configured to detect a logic level of the second input signal responsive to the second timing signal and the second reference voltage, wherein the second timing signal is related to the first timing signal, and wherein the second reference voltage is related to the first reference voltage;
a third receiver configured to receive the second input signal, a third timing signal and a third reference voltage and further configured to detect the logic level of the second input signal responsive to the third timing signal and the third reference voltage, wherein the third timing signal is related to the first timing signal, and wherein the third reference voltage is related to the first reference voltage; and
a control circuit configured to adjust at least one of the first timing signal and the first reference voltage responsive to output signals from the second and third receivers.

2. The apparatus of claim 1 , wherein each of the second and third receivers is configured to be a replica of the first receiver.

3. The apparatus of claim 1 , wherein at least one of the second timing signal and the second reference voltage is further related to a corresponding one of the third timing signal and the third reference voltage.

4. The apparatus of claim 1 ,
wherein at least one of the second and third timing signals is either advanced or delayed in phase with respect to the first timing signal, and
wherein at least one of the second and third reference voltages is either higher or lower than the first reference voltage.

5. The apparatus of claim 1 ,
wherein the second timing signal is either advanced or delayed in phase with respect to the first timing signal,
wherein the third timing signal is either delayed or advanced in phase with respect to the first timing signal,
wherein the second reference voltage is either higher or lower than the first reference voltage, and
wherein the third reference voltage is either lower or higher than the first reference voltage.

Assignees

• Micron Technology Inc

Inventors

• Hiraishi Atsushi

Classifications

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4099

  Dummy cell treatment; Reference voltage generators · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C7/1093

  Input synchronization · CPC title