Signal generator

Patent metadata

Field	Value
Publication number	US-10862489-B2
Application number	US-201916670394-A
Country	US
Kind code	B2
Filing date	Oct 31, 2019
Priority date	Oct 31, 2018
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

A signal generator comprises (i) a first set of capacitors at least partially switchably connectable for adjusting a frequency of an oscillator as part of a phase-locked loop and (ii) a second set of capacitors comprised in one or more oscillator control subsystems. A method of controlling the signal generator comprises: (i) acquiring a frequency lock in the phase-locked loop, (ii) calculating, in conjunction with the acquiring of the frequency lock, a systematic capacitance error of the first set of capacitors due to process, voltage, and temperature variations based on the frequency of the oscillator and a switching state of the first set of capacitors, and (iii) calibrating the one or more oscillator control subsystems using the systematic capacitance error, thereby compensating for process, voltage, and temperature variations common between the first set of capacitors and the second set of capacitors.

First claim

What is claimed is:

1. A method of controlling a signal generator, wherein the signal generator comprises (i) a first set of capacitors at least partially switchably connectable for adjusting a frequency of an oscillator as part of a phase-locked loop, and (ii) a second set of capacitors comprised in one or more oscillator control subsystems, the method comprising:
acquiring a frequency lock in the phase-locked loop;
calculating, in conjunction with the acquiring of the frequency lock, a systematic capacitance error of the first set of capacitors due to process, voltage, and temperature variations, wherein calculating the systematic capacitance error comprises:
calculating an actual capacitance of the first set of capacitors based on (i) the frequency of the oscillator and (ii) an inductance of an inductor of the oscillator,
calculating a nominal capacitance of the first set of capacitors based on a switching state of the first set of capacitors, and
calculating the systematic capacitance error based on the actual capacitance and the nominal capacitance; and

calibrating the one or more oscillator control subsystems using the systematic capacitance error, thereby compensating for process, voltage, and temperature variations common between the first set of capacitors and the second set of capacitors.

2. The method of claim 1 , wherein the one or more oscillator control subsystems comprises a modulation stage of the oscillator.

3. The method of claim 1 , wherein the signal generator further comprises a phase-detection stage for the phase-locked loop, and wherein the phase-detection stage comprises a time-to-digital converter.

4. The method of claim 3 , wherein the one or more oscillator control subsystems comprises a digital-to-time converter configured to produce a phase reference input to the phase-detection stage.

5. The method of claim 1 , wherein the one or more oscillator control subsystems comprises a phase-lock loop filter controlling a capacitor bank, the capacitor bank being at least partially switchably connectable for adjusting the frequency of the oscillator as part of the phase-locked loop, and the capacitor bank being comprised in the second set of capacitors.

6. The method of claim 1 , wherein the acquiring of the frequency lock occurs in a cycle-counting phase of the phase-locked loop.

7. The method of claim 1 , wherein the calibrating of the one or more oscillator control subsystems occurs after the acquiring of the frequency lock.

8. The method of claim 1 , wherein the calibrating of the one or more oscillator control subsystems occurs during the acquiring of the frequency lock.

9. The method of claim 1 , further comprising acquiring a phase lock in a phase-detection phase of the phase-locked loop, wherein the calibrating of the one or more oscillator control subsystems occurs before or during the acquiring of the phase lock.

10. The method of claim 1 , wherein the second set of capacitors are not part of the phase-locked loop.

11. The method of claim 1 , wherein the oscillator is a digitally controlled oscillator.

12. The method of claim 1 , wherein the phase-locked loop is an all-digital phase-locked loop.

13. A signal generator comprising:
a first set of capacitors at least partially switchably connectable for adjusting a frequency of an oscillator as part of a phase-locked loop;
a second set of capacitors comprised in one or more oscillator control subsystems; and
a processor or circuitry configured to:
calculate, in conjunction with acquiring of a frequency lock in the phase-locked loop, a systematic capacitance error of the first set of capacitors due to process, voltage, and temperature variations, wherein calculating the systematic capacitance error comprises:
calculating an actual capacitance of the first set of capacitors based on the (i) frequency of the oscillator and (ii) an inductance of an inductor of the oscillator,
calculating a nominal capacitance of the first set of capacitors based on a switch state of the first set of capacitors, and
calculating the systematic capacitance error based on the actual capacitance and the nominal capacitance; and

calibrate the one or more oscillator control subsystems using the systematic capacitance error, thereby compensating for process, voltage, and temperature variations common between the first set of capacitors and the second set of capacitors.

14. The signal generator of claim 13 , wherein the one or more oscillator control subsystems comprises a modulation stage of the oscillator.

15. The signal generator of claim 13 , further comprising a phase-detection stage for the phase-locked loop, wherein the phase-detection stage comprises a time-to-digital converter.

16. The signal generator of claim 15 , wherein the one or more oscillator control subsystems comprises a digital-to-time converter configured to produce a phase reference input to the phase-detection stage.

17. The signal generator of claim 13 , wherein the one or more oscillator control subsystems comprises a phase-lock loop filter controlling a capacitor bank, the capacitor bank being at least partially switchably connectable for adjusting the frequency of the oscillator as part of the phase-locked loop, and the capacitor bank being comprised in the second set of capacitors.

18. A wireless transceiver comprising the signal generator of claim 13 .

19. The signal generator of claim 13 , wherein the calibrating of the one or more oscillator control subsystems occurs after the acquiring of the frequency lock.

20. The signal generator of claim 13 , wherein the calibrating of the one or more oscillator control subsystems occurs during the acquiring of the frequency lock.

Assignees

• Stichting Imec Nederland

Inventors

• Van Den Heuvel Johan
• Mateman Paul

Classifications

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H03C3/0991

  including calibration means or calibration methods · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03C3/0941

  applying frequency modulation at more than one point in the loop · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title