Method and apparatus for measuring/compensating mismatches in digitally-controlled oscillator

Patent metadata

Field	Value
Publication number	US-8994467-B2
Application number	US-201313794774-A
Country	US
Kind code	B2
Filing date	Mar 11, 2013
Priority date	Apr 5, 2012
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

A digitally-controlled oscillator (DCO) includes a first capacitor array and a second capacitor array responsive to an integer part and a fractional part of a digital control word, respectively. The mismatch measurement of the DCO includes a first settling phase and a second settling phase. In the first settling phase, the first capacitor array is fixed to have one capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to a target value. In the second settling phase, the first capacitor array is fixed to have another capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to the same target value. The capacitor mismatches are estimated according to characteristic values derived from the digital control word adaptively adjusted in the first setting phase and the second setting phase.

First claim

What is claimed is:

1. A method for dealing with mismatches in a digitally-controlled oscillator (DCO), comprising:
performing at least one measurement operation, each comprising:
in a first settling phase, controlling a first capacitor array of the DCO to have a first capacitive value consistently, and controlling a second capacitor array of the DCO in a closed loop to make a frequency of the DCO locked to a target value, wherein the first capacitor array is responsive to an integer part of a digital control word, and the second capacitor array is responsive to a fractional part of the digital control word;
in a second settling phase, controlling the first capacitor array to have a second capacitive value consistently, and controlling the second capacitor array in the closed loop to make the frequency of the DCO locked to the target value, wherein the second capacitive value is different from the first capacitive value; and
deriving an estimation value from a difference value between a first characteristic value and a second characteristic value, wherein the first characteristic value is derived from the digital control word adaptively adjusted in the first settling phase, and the second characteristic value is derived from the digital control word adaptively adjusted in the second settling phase; and

estimating the mismatches according to at least the estimation value generated from the at least one measurement operation.

2. The method of claim 1 , wherein the first capacitor array is a thermometer coded capacitor array; the step of controlling the first capacitor array of the DCO to have the first capacitive value comprises: consistently enabling a first predetermined number of capacitors in the first capacitor array; the step of controlling the first capacitor array of the DCO to have the second capacitive value comprises: consistently enabling a second predetermined number of capacitors in the first capacitor array; and a difference between the second predetermined number and the first predetermined number is equal to one.

3. The method of claim 2 , wherein a plurality of measurement operations are performed for a plurality of capacitors in the first capacitor array, respectively; and regarding each of the capacitors in the first capacitor array, the capacitor is enabled in one of the first settling phase and the second settling phase, while disabled in the other of the first settling phase and the second settling phase.

4. The method of claim 1 , wherein the first capacitor array is a binary coded capacitor array; the step of controlling the first capacitor array of the DCO to have the first capacitive value comprises: consistently enabling first selected capacitors in the first capacitor array; the step of controlling the first capacitor array of the DCO to have the second capacitive value comprises: consistently enabling second selected capacitors in the first capacitor array; and a difference between an accumulated capacitive value of the first selected capacitors and an accumulated capacitive value of the second selected capacitors corresponds to a capacitive value of a smallest capacitor in the first capacitor array.

5. The method of claim 4 , wherein a plurality of measurement operations are performed for different combinations of first selected capacitors and second selected capacitors in the first capacitor array, respectively.

6. The method of claim 5 , wherein the measurement operations include at least one measurement operation having an accumulated capacitive value of first selected capacitors greater than an accumulated capacitive value of second selected capacitors, and at least one measurement operation having an accumulated capacitive value of first selected capacitors smaller than an accumulated capacitive value of second selected capacitors.

7. The method of claim 1 , further comprising:
determining a first compensation value according to the estimated mismatches and a specific integer part of the digital control word; and
adjusting a specific fractional part of the digital control word according to the first compensation value and a second compensation value such that an accumulated capacitor mismatch of selected capacitors in the first capacitor array that are enabled according to the specific integer part is compensated due to the first compensation value, and a systematic mismatch between capacitors in the first capacitor array and capacitors in the second capacitor array is compensated due to the second compensation value.

8. The method of claim 7 , further comprising:
checking if a predetermined criterion is satisfied; and
when the predetermined criterion is satisfied, increasing the specific fractional part by an adjustment value, and decreasing the specific integer part by the adjustment value, wherein the first compensation value is determined according to the decreased integer part, and the increased fractional part is adjusted according to the first compensation value and the second compensation value.

9. The method of claim 8 , wherein the predetermined criterion is satisfied when it is determined that the specific fractional part becomes negative when compensated by a compensation amount corresponding the specific integer part.

10. The method of claim 1 , further comprising:
receiving a control value derived from the fractional part;
performing a sigma-delta modulation (SDM) upon the control value to generate an SDM output; and
utilizing a dynamic element matching (DEM) circuit to transmit the SDM output to the second capacitor array of the DCO.

11. An apparatus for dealing with mismatches in a digitally-controlled oscillator (DCO), comprising:
a measurement apparatus, comprising:
a measuring circuit, arranged for performing at least one measurement operation, each comprising:
in a first settling phase, controlling a first capacitor array of the DCO to have a first capacitive value consistently, wherein a second capacitor array of the DCO is controlled in a closed loop to make a frequency of the DCO locked to a target value, the first capacitor array is responsive to an integer part of a digital control word, and the second capacitor array is responsive to a fractional part of the digital control word;
in a second settling phase, controlling the first capacitor array to have a second capacitive value consistently, wherein the second capacitor array is controlled in the closed loop to make the frequency of the DCO locked to the target value, and the second capacitive value is different from the first capacitive value; and
deriving an estimation value from a difference value between a first characteristic value and a second characteristic value, wherein the first characteristic value is derived from the digital control word adaptively adjusted in the first settling phase, and the second characteristic value is derived from the digital control word adaptively adjusted in the second settling phase; and

an estimating circuit, arranged for estimating the mismatches according to at least the estimation value generated from the at least one measurement operation performed by the measuring circuit.

12. The apparatus of claim 11 , wherein the first capacitor array is a thermometer coded capacitor array; and the measuring circuit is arranged to consistently enable a first predetermined number of capacitors in the first capacitor array in the first settling phase, and consistently enable a second predetermined number of capacitors in the first capacitor array in the second settling phase, where a difference between the second predetermined number and the first predetermined number is equal to one.

13. The apparatus of cl

Assignees

• Mediatek Singapore Pte Ltd

Inventors

• Lee Wen-Chang
• Shen Shih-Chi
• Chen Chii-Horng
• Guo Xiaochuan

Classifications

• H03B1/00

  Details · CPC title

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/095 Primary

  using a lock detector (H03L7/087 takes precedence) · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title