Functional block stacked 3dic and method of making same

Patent metadata

Field	Value
Publication number	US-2016190101-A1
Application number	US-201615060341-A
Country	US
Kind code	A1
Filing date	Mar 3, 2016
Priority date	Feb 20, 2014
Publication date	Jun 30, 2016
Grant date	—

Abstract

An embodiment device package includes a fan-out redistribution layer (RDL), a device over and bonded to the fan-out RDL, and a molding compound over the fan-out RDL and extending along sidewalls of the device. The device includes a first functional tier having a first metallization layer and a second functional tier having a second metallization layer. The second functional tier is bonded to the first functional tier. The device further includes an interconnect structure electrically connecting the first metallization layer to the second metallization layer. The interconnect structure includes an inter-tier via (ITV) at least partially disposed in both the first functional tier and the second functional tier, and the ITV contacts the first metallization layer.

First claim

What is claimed is:

1 . A device package comprising:
a first die comprising:
a first substrate;
a first active device on the first substrate; and
a first interconnect structure comprising a first conductive feature electrically connected to the first active device;
a second die directly bonded to the first die, wherein the second die comprises:
a second substrate;
a second active device on the second substrate; and
a second interconnect structure comprising a second conductive feature electrically connecting the second active device;
a conductive via at least partially disposed in both the first interconnect structure and the second interconnect structure, wherein the conductive via electrically connects the first conductive feature to the second conductive feature; and fan-out redistribution layers extending laterally past the first die and the second die, wherein the fan-out redistribution layers are electrically connected to the first conductive feature, the second conductive feature, and the conductive via.

2 . The device package of claim 1 , further comprising a bonding layer bonding the first die to the second die, wherein the bonding layer is substantially free of any electrical connectors, and wherein the bonding layer comprises an oxide, poly or single crystal silicon (Si), silicon nitride (SiN), silicon carbide (SiC), titanium (Ti), copper (Cu), titanium nitride (TiN), alloys thereof, or a combination thereof.

3 . The device package of claim 1 , wherein the first substrate and the second substrate comprise different thicknesses.

4 . The device package of claim 1 further comprising a molding compound extending along sidewalls of the first die and the second die.

5 . The device package of claim 4 further comprising a through-via extending through the molding compound, wherein the through-via electrically connects the fan-out redistribution layers to the first die and the second die.

6 . The device package of claim 4 further comprising a passive device adjacent the first die and electrically connected to the fan-out redistribution layers, wherein the molding compound extends along sidewalls of the passive device.

7 . The device package of claim 1 , further comprising a plurality of pillar bumps between the first die and the fan-out redistribution layers, wherein the plurality of pillar bumps electrically connect the fan-out redistribution layers to the first die and the second die.

8 . The device package of claim 1 further comprising:
a conductive line on an opposing side of the second substrate as the first die, wherein the conductive via extends from the conductive line through the second die to the first conductive feature; and
an additional conductive via extending from the conductive line to second conductive feature, wherein the additional conductive via is electrically connected to the conductive via through the conductive line.

9 . The device package of claim 1 , the conductive via contacts both the first conductive feature and the second conductive feature.

10 . The device package of claim 9 , wherein a first end of the conductive via contacts the first conductive feature and a second end of the conductive via contacts the second conductive feature.

11 . A method comprising:
directly bonding a first die to a second die to form a device; forming an interconnect structure at least partially disposed in the first die and the second die, wherein the interconnect structure electrically connects first functional circuits in the first die to second functional circuits in the second die; forming one or more pillar bumps on the device; electrically connecting the device to one or more fan-out redistribution layers using the one or more pillar bumps; and electrically connecting one or more package components to the device through the one or more fan-out redistribution layers.

12 . The method of claim 11 , wherein the one or more pillar bumps is electrically connected to the device without any intervening under bump metallurgy or contact pad features.

13 . The method of claim 11 , wherein one or more package components comprises a passive device, an active device, a device chip, a package substrate, an interposer, another device package, or a combination thereof.

14 . The method of claim 11 , wherein the second die a semiconductor substrate, and wherein the method further comprises thinning the semiconductor substrate after bonding the first die to the second die.

15 . The method of claim 11 , wherein bonding the first die to the second die comprises using a semiconductor substrate of the first die as structural support without using an additional carrier for structural support.

16 . A method comprising:
bonding a first die to a second die; electrically connecting a first conductive feature in the first die to a second conductive feature in the second die with a first conductive via, wherein the first conductive via extends at least partially through the first die and the second die; bonding the first die and the second die to a fan-out redistribution layer, wherein the fan-out redistribution layer extends laterally past the first die and the second die; and dispensing a molding compound over the fan-out redistribution layer, wherein the molding compound extends along sidewalls of the first die and the second die.

17 . The method of claim 16 , wherein electrically connecting the first conductive feature to the second conductive feature comprises patterning a via opening using a single photomask, wherein the via opening extends through the second die and at least partially through the first die, and wherein the via opening at least partially exposes the first conductive feature and the second conductive feature.

18 . The method of claim 17 , further comprising forming a RDL over the second die, wherein forming the RDL and electrically connecting the first conductive feature to the second conductive feature further comprises:
forming a dielectric layer over the second die; patterning a trench opening in the dielectric layer, wherein the trench opening is connected to the via opening; forming a barrier layer over sidewalls and bottom surfaces of the trench opening and the via opening; removing lateral portions of the barrier layer; and filling the trench opening and the via opening with a conductive material.

19 . The method of claim 16 further comprising:
forming a redistribution layer over the second die, wherein the first conductive via is electrically connected to the redistribution layer; and
forming one or more pillar bumps on the redistribution layer, wherein the one or more pillar bumps electrically connects the first die and the second die to the fan-out redistribution layers.

20 . The method of claim 19 further comprising forming a second conductive via extending through the molding compound, wherein the second conductive via electrically connects the one or more pillar bumps to the fan-out redistribution layers.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yu Chen-Hua
• Yee Kuo-Chung
• Tung Chih-Hang

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title