Structure and formation method for chip package

Patent metadata

Field	Value
Publication number	US-10163859-B2
Application number	US-201514919378-A
Country	US
Kind code	B2
Filing date	Oct 21, 2015
Priority date	Oct 21, 2015
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, and the dielectric layer is substantially made of a semiconductor oxide material. The chip package further includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip.

First claim

What is claimed is:

1. A chip package, comprising:
a semiconductor chip;
a semiconductor die hybrid bonded to the semiconductor chip at an interface, wherein at the interface a first dielectric material of the semiconductor die is bonded to a second dielectric material of the semiconductor chip and wherein a first metallic material of the semiconductor die is bonded to a second metallic material of the semiconductor chip;
a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, wherein the dielectric layer is substantially made of a semiconductor oxide material throughout the dielectric layer;
a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting to a conductive pad of the semiconductor chip; and
a second conductive feature penetrating through the semiconductor substrate of the semiconductor die and being in physical contact with a conductive portion of a metallization layer adjacent to the semiconductor substrate of the semiconductor die, wherein the second conductive feature has a surface facing the conductive portion of the metallization layer of the semiconductor die and also facing the semiconductor chip.

2. The chip package as claimed in claim 1 , wherein the dielectric layer is in direct contact with the semiconductor die.

3. The chip package as claimed in claim 1 , wherein the conductive feature penetrates through an interconnection structure of the semiconductor die to be in electrical contact with the conductive pad of the semiconductor chip.

4. The chip package as claimed in claim 1 , further comprising a third conductive feature penetrating through the dielectric layer and in electrical contact with a second conductive pad of the semiconductor chip.

5. The chip package as claimed in claim 1 , further comprising:
a bonding pad between the semiconductor chip and the semiconductor die; and
a third conductive feature underlying the bonding pad and physically connecting the bonding pad, wherein the third conductive feature is between the bonding pad and the semiconductor chip and is electrically connected to a second conductive pad of the semiconductor chip.

6. The chip package as claimed in claim 5 , further comprising:
a second bonding pad between the semiconductor chip and the semiconductor die; and
a fourth conductive feature underlying the second bonding pad and isolated from the second bonding pad, wherein the fourth conductive feature is between the bonding pad and the semiconductor chip and is electrically connected to a third conductive pad of the semiconductor chip.

7. The chip package as claimed in claim 6 , wherein the third conductive feature is a testing pad.

8. The chip package as claimed in claim 6 , wherein top surfaces of the bonding pad and the second bonding pad are substantially coplanar.

9. The chip package as claimed in claim 1 , further comprising an insulating element between the conductive feature and the semiconductor substrate of the semiconductor die.

10. The chip package as claimed in claim 1 , wherein a portion of the dielectric layer is sandwiched between the semiconductor die and the semiconductor chip.

11. The chip package as claimed in claim 1 , wherein the dielectric layer is polymer-free.

12. The chip package as claimed in claim 1 , wherein the conductive feature is a unitary and continuous material from a topmost edge of the conductive feature to a bottommost edge of the conductive feature.

13. The chip package of claim 1 , wherein a portion of the conductive feature that penetrates through the semiconductor substrate of the semiconductor die and physically connects to the conductive pad of the semiconductor chip has straight sidewalls.

14. A chip package, comprising:
a semiconductor chip;
a semiconductor die over the semiconductor chip;
a dielectric layer encapsulating and covering at least the side surfaces of the semiconductor die, wherein the dielectric layer is free of polymer material;
a conductive feature penetrating through a semiconductor substrate of the semiconductor chip, wherein each cross section of the conductive feature that is parallel with a first major surface of the semiconductor die is centered on a longitudinal axis of the conductive feature, wherein a first material of the conductive feature extends through a metallization layer of the semiconductor die between the semiconductor chip and the semiconductor substrate and wherein the first material has a first width as it extends through the metallization layer of the semiconductor die and has a second width larger than the first width on a side of the semiconductor die opposite the semiconductor chip; and
a connector over the semiconductor substrate and electrically connected to the conductive feature, wherein the semiconductor chip is between the semiconductor die and the connector.

15. The chip package as claimed in claim 14 , wherein there is no molding compound between the dielectric layer and the semiconductor die.

16. The chip package as claimed in claim 14 , further comprising a second conductive feature penetrating through a semiconductor substrate of the semiconductor die.

17. The chip package as claimed in claim 14 , further comprising a second conductive feature penetrating through the dielectric layer.

18. The chip package as claimed in claim 14 , further comprising:
a bonding pad between the semiconductor chip and the semiconductor die; and
a second conductive feature underlying the bonding pad and physically connecting the bonding pad, wherein the second conductive feature is between the bonding pad and the semiconductor chip and is electrically connected to a second conductive pad of the semiconductor chip.

19. The chip package as claimed in claim 18 , further comprising:
a second bonding pad between the semiconductor chip and the semiconductor die; and
a third conductive feature underlying the second bonding pad and isolated from the second bonding pad, wherein the third conductive feature is between the bonding pad and the semiconductor chip and is electrically connected to a third conductive pad of the semiconductor chip.

20. The chip package as claimed in claim 14 , wherein the conductive feature is a unitary and continuous material from a topmost edge of the conductive feature to a bottommost edge of the conductive feature.

21. A chip package, comprising:
a semiconductor chip;
a semiconductor die bonded to the semiconductor chip, wherein the semiconductor die is in direct contact with the semiconductor chip;
a polymer-free dielectric encapsulating and covering at least the side surfaces of the semiconductor die; and
a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip, wherein the conductive feature comprises a first material which continuously extends from a first point within the semiconductor substrate of the semiconductor die to a second point within the semiconductor chip, wherein the first material extends through a metallization layer adjacent to the semiconductor substrate of the semiconductor die between the semiconductor chip and the semiconductor substrate and wherein the first material has a first width as it extends through the metallization layer of the semiconductor die and has a second width larger than the first width on a side of the semiconductor die opposite the semiconductor chip.

22. The chip package

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Chen Ming-Fa
• Yeh Sung-Feng

Classifications

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0253

  comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0238

  comprising etching via holes through pads or through electrodes · CPC title