Method for forming at least one electrical discontinuity in an integrated circuit, and corresponding integrated circuit

Patent metadata

Field	Value
Publication number	US-10861802-B2
Application number	US-201816208253-A
Country	US
Kind code	B2
Filing date	Dec 3, 2018
Priority date	Nov 22, 2016
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.

First claim

The invention claimed is:

1. A method, comprising:
producing, above a semiconductor substrate and encapsulated in an insulating region, a multitude of electrically conductive pads situated between source-drain regions in the semiconductor substrate and a first metallization level over the semiconductor substrate, respectively;
wherein producing includes:
electrically connecting first pads of said multitude of pads with corresponding first source-drain regions; and
insulating at least one second pad from electrical contact with a corresponding second source-drain region so as to form said at least one electrical discontinuity;
wherein the first and second source-drain regions are parts of a transistor, and wherein the at least one electrical discontinuity is dimensioned such that the transistor is permanently turned off.

2. The method according to claim 1 , wherein producing comprises:
producing the first pads encapsulated in said insulating region;
locally etching said insulating region at the location of said at least one second pad so as to form at least one orifice leading to said corresponding second source-drain region;
lining an internal wall of said at least one orifice and said second source-drain region with an insulating layer having a material composition identical to that of a part of said insulating region; and
filling said at least one orifice lined with the insulating layer with a filler material having a material composition identical to that of the first pads, so as to form said at least one second pad.

3. The method according to claim 2 , wherein locally etching and lining are configured to form said at least one orifice lined with the insulating layer to have a cross-sectional size such that said at least one second pad has a cross-sectional size analogous to a cross-sectional size of each first pad.

4. The method according to claim 1 , further comprising forming said first metallization level over the insulating region to include a first metal line in electrical contact with one of the first pads and a second electrical line in electrical contact with the at least one second pad.

5. The method of claim 1 , wherein the at least one electrical discontinuity is formed so as to prevent charge carriers from moving from the second source-drain region to the second pad.

6. A method, comprising:
forming source-drain regions in a semiconductor substrate;
forming a first metallization level over the semiconductor substrate;
forming a plurality of electrically conductive pads between the source-drain regions and the first metallization level;
encapsulating the plurality of electrically conductive pads with an insulating region;
electrically connecting a first pad of the plurality of electrically conductive pads to a corresponding first source-drain region; and
insulating a second pad of the plurality of electrically conductive pads from a corresponding second source-drain region so as to form at least one electrical discontinuity;
wherein the first and second source-drain regions are parts of a transistor, and
wherein the at least one electrical discontinuity is dimensioned such that the transistor is permanently turned off.

7. The method of claim 6 , further comprising
defining at least one orifice in the insulating region at a location of the second pad to expose the second source-drain region;
lining an internal wall of the at least one orifice and the second source-drain region with an insulating layer; and
filling the at least one orifice with a filler material to form the second pad of the plurality of electrically conductive pads.

8. The method of claim 7 , wherein the at least one orifice as lined with the insulating layer has a cross-sectional size such that the second pad of the plurality of electrically conductive pads has a cross-sectional size equal to a cross sectional size of the first pad of the plurality of electrically conductive pads.

9. The method of claim 7 , wherein the insulating layer has a same composition as at least a portion of the insulating region.

10. The method of claim 7 , wherein the filler material has a same composition as that of the first pad of the plurality of electrically conductive pads.

11. The method of claim 6 , wherein the first metallization level is formed to include a first metal line in electrical contact with the first pad of the plurality of electrically conductive pads and a second electrical line in contact with the second pad of the plurality of electrically conductive pads.

12. The method of claim 6 , wherein electrically connecting the first pad to the first source-drain region is performed by electrically connecting the first pad to a silicided region of the first source-drain region.

13. The method of claim 6 , wherein the at least one electrical discontinuity is formed so as to prevent charge carriers from moving from the second source-drain region to the at least one second pad.

14. A method comprising:
forming source-drain regions in a semiconductor substrate;
forming a first metallization level over the semiconductor substrate;
forming a plurality of electrically conductive pads between the source-drain regions and the first metallization level;
encapsulating the plurality of electrically conductive pads with an insulating region;
electrically connecting a first pad of the plurality of electrically conductive pads to a corresponding first source-drain region; and
insulating a second pad of the plurality of electrically conductive pads from a corresponding second source-drain region so as to form at least one electrical discontinuity;
wherein the first pad of the plurality of electrically conductive pads is formed by etching using a mask that has a first mask opening for the first pad of the plurality of electrically conductive pads but lacks a second mask opening for the second pad of the plurality of electrically conductive pads.

15. The method of claim 14 , wherein the at least one electrical discontinuity is formed so as to prevent charge carriers from moving from the second source-drain region to the second pad.

16. A method, comprising:
producing, above a semiconductor substrate and encapsulated in an insulating region, a multitude of electrically conductive pads situated between source-drain regions in the semiconductor substrate and a first metallization level over the semiconductor substrate, respectively;
wherein producing includes:
electrically connecting a first pad of said multitude of pads with a corresponding first source-drain region; and
insulating a second pad from electrical contact with a corresponding second source-drain region so as to form at least one electrical discontinuity;
wherein the first pad is formed by etching using a mask that has a first mask opening for the first pad but lacks a second mask opening for the second pad.

17. The method of claim 16 , wherein the at least one electrical discontinuity is formed so as to prevent charge carriers from moving from the second source-drain region to the second pad.

Assignees

• St Microelectronics Rousset

Inventors

• Rivero Christian
• Fornara Pascal
• Bouton Guilhem
• Lisart Mathieu

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title