Radar front end with RF oscillator monitoring

Patent metadata

Field	Value
Publication number	US-10859674-B2
Application number	US-201816014044-A
Country	US
Kind code	B2
Filing date	Jun 21, 2018
Priority date	Jun 21, 2017
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

An apparatus is described that, according to an exemplary embodiment, has an RF oscillator for generating an RF oscillator signal at a first frequency and a frequency divider having a division ratio that is fixed during operation. The frequency divider is supplied with the RF oscillator signal and is configured to provide an oscillator signal at a second frequency. The apparatus further has a monitor circuit, to which the oscillator signal at the second frequency is supplied and which is configured to measure the second frequency and to provide at least one digital value that is dependent on the second frequency of the oscillator signal. The at least one digital value is provided on a test contact.

First claim

What is claimed is:

1. An apparatus, comprising:
an RF oscillator configured to generate an RF oscillator signal at a first frequency;
a frequency divider having a division ratio that is fixed during operation, to which the RF oscillator signal is supplied and which is configured to provide a second oscillator signal at a second frequency;
a monitor circuit, to which the second oscillator signal at the second frequency is supplied and which is configured to measure the second frequency and provide at least one digital value that is dependent on the second frequency of the second oscillator signal;
a ramp generator configured to generate a ramp signal and configured to generate a synchronization signal for the monitor circuit, the synchronization signal synchronizes a measurement of the second frequency by the monitor circuit to the generation of the ramp signal; and
at least one test contact, on which the at least one digital value is provided.

2. The apparatus according to claim 1 , wherein:
the RF oscillator is connected in a phase locked loop.

3. The apparatus according to claim 2 , wherein:
the ramp generator is coupled to the phase locked loop such that the first frequency is adjusted according to the ramp signal.

4. The apparatus according to claim 1 , wherein:
the monitor circuit is configured to count a number of clock cycles of the second oscillator signal within a time window stipulated by the synchronization signal.

5. The apparatus according to claim 2 , wherein:
the frequency divider is connected in a feedback loop of the phase locked loop.

6. The apparatus according to claim 1 , wherein:
the RF oscillator is a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO).

7. The apparatus according to claim 1 , wherein:
the monitor circuit is configured to count a number of clock cycles of the second oscillator signal within a time window, and
the monitor circuit is configured to check whether the number of clock cycles is in a desired range.

8. The apparatus according to claim 7 , wherein:
the at least one digital value comprises at least one of the following:
a Boolean value indicating whether the counted number of clock cycles is in the desired range; and
a digital word representing the counted number of clock cycles.

9. The apparatus according to claim 8 , further comprising:
a communication interface configured to make the digital word available as a serial or parallel data stream on the at least one test contact.

10. The apparatus according to claim 1 , wherein the frequency divider is a fixed frequency divider and the division ratio is fixed at a constant value throughout a generation of the ramp signal via the ramp generator.

11. The apparatus according to claim 10 , wherein:
the synchronization signal defines a measurement time interval that coincides with a portion of the ramp signal selected for monitoring, wherein the measurement time interval is defined by a first transition edge of the synchronization signal and a second transition edge of the synchronization signal, and
the monitor circuit is configured to enable measuring of the second frequency in response to detecting the first transition edge of the synchronization signal and disable measuring of the second frequency in response to detecting the second transition edge of the synchronization signal.

12. The apparatus according to claim 11 , wherein the portion of the ramp signal selected for monitoring is a specific frequency ramp of the ramp signal.

13. The apparatus according to claim 12 , wherein the portion of the ramp signal selected for monitoring is defined by a minimum oscillator frequency and a maximum oscillator frequency of the specific frequency ramp.

14. The apparatus according to claim 11 , wherein the monitor circuit is configured to calculate an average value of the second frequency measured during the measurement time interval, and convert the average value of the second frequency into an average value of the first frequency.

15. The apparatus according to claim 11 , wherein the monitor circuit is configured to count a total number of clock cycles of the second oscillator signal during the measurement time interval, compare the total number of clock cycles to a tolerance range to determine whether the total number of clock cycles are within or outside the tolerance range, and generate a digital value based on whether the total number of clock cycles is within or outside the tolerance range.

16. The apparatus according to claim 15 , wherein the monitor circuit includes a counter that is configured to count the total number of clock cycles of the second oscillator signal during the measurement time interval, wherein the counter is activated in response to the first transition edge of the synchronization signal and deactivated in response to the second transition edge of the synchronization signal.

17. The apparatus according to claim 11 , wherein the monitor circuit is configured to count a total number of clock cycles of the second oscillator signal during the measurement time interval, and generate a digital value representative of the total number of clock cycles of the second oscillator signal.

18. A method, comprising:
actuating an RF oscillator such that the RF oscillator generates an RF oscillator signal at a first frequency;
generating a second oscillator signal at a second frequency from the first RF oscillator signal using a frequency divider having a division ratio that is fixed during operation;
generating a ramp signal;
generating a synchronization signal;
measuring the second frequency based on the synchronization signal and the ramp signal, wherein the synchronization signal synchronizes the measuring of the second frequency to the ramp signal;
providing at least one digital value that is dependent on the measured second frequency of the second oscillator signal; and
providing the at least one digital value on a test contact.

19. The method according to claim 18 , wherein providing the at least one digital value comprises:
checking whether the measured second frequency is consistent with a desired value or differs from the desired value by less than a maximum permitted difference,
wherein the at least one digital value indicates the result of the check.

20. The method according to claim 18 , wherein:
the first frequency and the second frequency vary during the measuring.

21. The method according to claim 18 , wherein:
the first frequency and the second frequency rise or fall in accordance with a defined frequency ramp, and
a time window in which the second frequency is measured is in sync with the frequency ramp.

22. The method according to claim 18 , wherein measuring the second frequency comprises:
counting a number of clock cycles of the second oscillator signal during a time window; and
storing the number of clock cycles counted up to an end of the time window.

23. The method according to claim 18 , wherein measuring the second frequency comprises:
counting a number of clock cycles of the second oscillator signal during a time window; and
storing, for at least one measurement time before expiry of the time window, the number of clock cycles counted up to a respective measurement time.

24. The method according to claim 23 , wherein providing the at least one digital value comprises:
comparing the number of clock cycles stored for the at least one m

Assignees

• Infineon Technologies Ag

Inventors

• Greslehner-Nimmervoll Bernhard
• Krebelder Georg
• Schrattenecker Jochen O

Classifications

• G01S13/931 Primary

  of land vehicles · CPC title

• H03L7/193

  the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider · CPC title

• H03L7/06

  using a reference signal applied to a frequency- or phase-locked loop · CPC title

• H03C3/0925

  applying frequency modulation at the divider in the feedback loop · CPC title

• H03C3/095

  applying frequency modulation to the loop in front of the voltage controlled oscillator · CPC title