Apparatus and method for evaluating the performance of a system in a control loop

Patent metadata

Field	Value
Publication number	US-9594100-B2
Application number	US-201314020404-A
Country	US
Kind code	B2
Filing date	Sep 6, 2013
Priority date	Sep 6, 2013
Publication date	Mar 14, 2017
Grant date	Mar 14, 2017

Abstract

A monitoring circuit for monitoring the performance of a phase locked loop having a divider therein, the divider comprising at least a first counter, the monitoring circuit comprising at least one memory element for capturing a value of the first counter after a predetermined time from a system event in the operation of the phase locked loop, a variability calculator for comparing a value of the counter with a preceding value of the counter to calculate a variation, and a circuit responsive to the estimate of variation for outputting a status signal.

First claim

What is claimed is:

1. A monitoring circuit electrically connectable to a phase locked loop (PLL) and configured to monitor performance of the PLL, the monitoring circuit comprising:
at least one memory element configured to capture a value of a first counter of a divider of the PLL after a predetermined time from a system event in the operation of the PLL; and
a variability calculator configured to compare a value of the first counter with a preceding value of the first counter to calculate a first value representative of a difference in values of the first counter, wherein the variability calculator is further configured to sum the first value from a plurality of observations of the operation of the PLL to generate a sum, wherein the monitoring circuit is configured to compare the sum with a threshold value and to output a status signal indicating a locked status of the PLL.

2. The monitoring circuit of claim 1 , wherein the divider of the PLL is a fractional divider comprising the first counter and a second counter.

3. The monitoring circuit of claim 1 , wherein the system event corresponds to at least one of setting the first counter to an initial value at the commencement of a cycle of the PLL or receipt of a clock signal.

4. The monitoring circuit of claim 1 , wherein the at least one memory element comprises at least one latch configured to latch an output of the first counter.

5. The monitoring circuit of claim 1 , wherein the at least one memory element comprises two series connected latches, and wherein the variability calculator comprises a subtractor configured to calculate the first value, and wherein the first value is representative of a difference in values held by the two series connected latches.

6. The monitoring circuit of claim 1 , further comprising at least one counter or timer configured to determine at least one of a number of operating cycles of the PLL that the PLL is monitored for or a duration that the PLL is monitored for.

7. A communication device including the monitoring circuit of claim 1 .

8. The monitoring circuit of claim 1 , in which transitions of a system clock are synchronized with transitions of the divider or a prescaler within the PLL.

9. The monitoring circuit of claim 1 , wherein the variability calculator is configured to compute a sum of variations over at least one of a first number of clock pulses or over a first time period.

10. The monitoring circuit of claim 9 , in which the monitoring circuit is configured to monitor the output of the variability calculator over an observation window, and a maximum modulus output of the variability calculator is compared with the threshold value.

11. The monitoring circuit of claim 10 , wherein the monitoring circuit is configured to adjust a length of the observation window.

12. The monitoring circuit of claim 9 , wherein the monitoring circuit is configured to adjust at least one of the first number of clock pulses or the first time period.

13. An electronic system comprising the monitoring circuit of claim 1 and the PLL, wherein the monitoring circuit is electrically connected to the PLL.

14. A circuit electrically connectable to a system wherein a counter within the system counts a parameter of the system, said counter being periodically reset in response to a system event and wherein variation in a value counted by the counter after a predetermined time from the system event is indicative of variability within the system, the circuit comprising:
one or more memory elements configured to store at least one value of the counter;
a variability calculating circuit configured to:
compare a value of the counter with a preceding value of the counter to generate a comparison result;
accumulate the comparison result for a first number of times to generate a first accumulated result; and
accumulate the first accumulated result for a second number of times to generate a second accumulated result; and

an output circuit configured to output a status signal indicating a lock status of the system in response to the second accumulated result.

15. An electronically-implemented method of monitoring performance of a phase locked loop (PLL), the method comprising:
repeatedly obtaining a value of a first counter of the PLL after a predetermined time from a trigger event, wherein the first counter is part of a fractional divider;
comparing consecutive counter values for a first number of times;
processing the first number of comparisons to obtain a measure of variability; and
outputting a lock detect signal indicative of a locked status of the PLL based on said processing,
wherein the method is performed by electronic circuitry.

16. The electronically-implemented method of claim 15 , in which said processing comprises summing the first number of comparisons a second number of times, and comparing a result of said summing with a range of values to determine a state of the lock detect signal.

17. The electronically-implemented method of claim 16 , wherein the second number is configurable.

18. The electronically-implemented method of claim 15 , wherein the first number is configurable.

19. An apparatus comprising:
a phase-locked loop comprising a prescaler and a fractional divider, the fractional divider comprising a first counter electrically coupled to the prescaler; and
a synchronization circuit configured to generate a synchronized counter signal based at least in part on an output of the prescaler and an output of the first counter, wherein the synchronized counter signal corresponds to the output of the first counter, and wherein transitions of the synchronized counter signal are synchronized with transitions of the output of the prescaler.

20. The apparatus of claim 19 , wherein a frequency of the prescaler output is higher than a frequency of the first counter output.

Assignees

• Analog Devices Global

Inventors

• Khan Muhammad Kalimuddin
• Mulvaney Kenneth J
• Deeney Michael
• Kearney Niall Kevin

Classifications

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• G01R23/02 Primary

  Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage · CPC title

• H03L7/1974

  for fractional frequency division · CPC title

• H03L7/095 Primary

  using a lock detector (H03L7/087 takes precedence) · CPC title

• H03L7/193

  the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider · CPC title