Method of generating self-test signals, corresponding circuit and apparatus

Patent metadata

Field	Value
Publication number	US-2018188317-A1
Application number	US-201715691381-A
Country	US
Kind code	A1
Filing date	Aug 30, 2017
Priority date	Jan 3, 2017
Publication date	Jul 5, 2018
Grant date	—

Abstract

A radio-frequency receiver includes built-in-self-test (BIST) circuitry which generates a self-test signal. A local oscillator signal is divided. A self-test oscillation signal is generated, based, at least in part, on the frequency-divided local oscillation signal. The self-test signal is generated based on the self-test oscillation signal. The BIST circuitry includes a divider, which divides the self-test oscillation signal. The frequency-divided local oscillation signal and the divided self-test oscillation signal are used to perform one or more of generating the self-test oscillation signal and controlling the generation of the self-test oscillation signal. The radio-frequency receiver may be an automotive radar receiver.

First claim

1 . A method, comprising:
applying frequency division to a local oscillator signal of a radio-frequency receiver, producing a frequency-divided signal; and generating a self-test signal of the radio-frequency receiver, the generating of the self-test signal of the radio-frequency receiver including one or more of:
generating the self-test signal based on the frequency-divided signal; and
monitoring generation of the self-test signal using the frequency-divided signal.

2 . The method of claim 1 , comprising:
generating said local oscillator signal using a first oscillator, wherein the generating the self-test includes generating a second oscillating signal using a second oscillator, and the generating the second oscillating signal includes one or more of:
controlling the second oscillator based on the frequency-divided signal; and
monitoring the generation of the second oscillating signal using the frequency-divided signal.

3 . The method of claim 2 , comprising:
setting frequencies of said first oscillator and said second oscillator based on a common coarse tuning signal; and fine-tuning the frequencies of said first oscillator and said second oscillator based on respective fine tuning signals.

4 . The method of claim 3 wherein one or more of the respective fine tuning signals is produced using a digital-to-analog converter.

5 . The method of claim 2 , comprising:
selectively tuning a frequency of said second oscillator, producing chirp modulation of said self-test signal.

6 . The method of claim 2 , comprising:
applying frequency division to said local oscillator signal (TX/LO) and said second oscillating signal to produce respective frequency-divided oscillating signals; and monitoring a frequency of said second oscillating signal, the monitoring including comparing said respective frequency-divided oscillating signals.

7 . The method of claim 1 , comprising:
generating the self-test signal using a phase-locked loop (PLL) circuit having an output oscillator, an input comparator and a loop divider between said output oscillator and said input comparator; and supplying to said input comparator of the PLL circuit said frequency-divided signal.

8 . The method of claim 7 , comprising:
delaying the frequency-divided signal provided to said input comparator of the PLL circuit.

9 . The method of claim 7 , comprising:
selectively varying a division factor of said loop divider, varying a frequency of said self-test signal.

10 . The method of claim 1 , comprising:
mixing the local oscillator signal with a received signal received by the radio-frequency receiver.

11 . A circuit, comprising:
a first frequency divider, which, in operation, frequency divides a first oscillation signal, generating a first frequency-divided signal; and self-test signal generation circuitry, which, in operation, generates a receiver self-test signal, the generating of the receiver self-test signal including one or more of:
generating the self-test signal based on the first frequency-divided signal; and
monitoring generation of the self-test signal using the first frequency-divided signal.

12 . The circuit of claim 11 , comprising:
a first oscillator, which, in operation, generates the first oscillation signal, wherein the self-test signal generation circuitry includes a second oscillator, which, in operation, generates a second oscillation signal, and the generating the second oscillation signal includes one or more of;
controlling the second oscillator based on the first frequency-divided signal; and
monitoring the generation of the second oscillating signal using the first frequency-divided signal.

13 . The circuit of claim 12 wherein:
a frequency of the first oscillator is set based on a common coarse tuning signal and a first fine-tuning signal; and
a frequency of the second oscillator is set based on the common coarse tuning signal and a second fine-tuning signal.

14 . The circuit of claim 13 , comprising:
a digital-to-analog converter, which, in operation, generates one or both of the first fine-tuning signal and the second fine-tuning signal.

15 . The circuit of claim 12 wherein the self-test signal generation circuitry, in operation, selectively tunes a frequency of the second oscillator, producing chirp modulation of the self-test signal.

16 . The circuit of claim 12 , wherein the self-test signal generation circuitry includes a second frequency divider, which, in operation frequency divides the second oscillation signal, producing a second frequency-divided signal, and the self-test signal generation circuitry, in operation, monitors the generation of self-test signal, the monitoring including comparing the first frequency-divided signal with the second frequency-divided signal.

17 . The circuit of claim 11 wherein the self-test signal generating circuitry includes a phase-locked loop, the phase-locked loop having:
an output oscillator;
an input comparator; and
a loop divider coupled between the output oscillator and the input comparator, wherein the input comparator is coupled to an output of the first frequency divider.

18 . The circuit of claim 17 , comprising:
a delay circuit coupled between the output of the first frequency divider and an input of the input comparator.

19 . The circuit of claim 17 wherein a division factor of the loop divider is adjustable and, in operation, varying the division factor of the loop divider varies a frequency of the self-test signal.

20 . The circuit of claim 11 , comprising:
a mixer, which, in operation, mixes the first oscillation signal with a received radio-frequency signal.

21 . A system, comprising:
an input node, which, in operation, receives a frequency-divided local oscillation signal; a self-test oscillator, which, in operation, generates a self-test oscillation signal, based, at least in part, on the received frequency-divided local oscillation signal; a divider, which, in operation, divides the self-test oscillation signal; and a test-signal output node, which, in operation, outputs a receiver self-test signal based on the self-test oscillation signal.

22 . The system of claim 21 wherein the self-test oscillator is coupled to one or more of:
the input node; and
a control signal generated based on the received frequency-divided local oscillation signal.

23 . The system of claim 21 , comprising:
a local oscillator, which, in operation, generates a local oscillation signal; and a frequency divider coupled to the local oscillator, which, in operation, receives the local oscillation signal and generates the frequency-divided local oscillation signal.

24 . The system of claim 21 , comprising:
a phase-locked loop including the self-test oscillator, the divider and a comparator, wherein the comparator is coupled to the input node and to an output of the divider and the self-test oscillator is coupled to an output of the comparator.

25 . The system of claim 24 , comprising one or more of:
a filter coupled between the comparator and the self-test oscillator; a delay circuit coupled between the input node and the comparator; a lock detector, which, in operation, generates a signal indicative of a lock condition of the phase-locked loop; a variable-gain amplifier coupled between the self-test oscillator and the test-signal output node; a power detector, which, in operation, ge

Assignees

• St Microelectronics Srl

Inventors

• Maiellaro Giorgio
• Scuderi Angelo
• Bruno Angela
• Scaccianoce Salvatore

Classifications

• H04B17/0085 Primary

  using test signal generators · CPC title

• G01R31/2832

  Specific tests of electronic circuits not provided for elsewhere (G01R31/2801, G01R31/316 take precedence) · CPC title

• H03C3/0916

  with frequency divider or counter in the loop · CPC title

• H03C3/0958

  applying frequency modulation by varying the characteristics of the voltage controlled oscillator · CPC title

• G01R31/2884 Primary

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title