Test methods for packaged integrated circuits

Patent metadata

Field	Value
Publication number	US-10859630-B2
Application number	US-201715813553-A
Country	US
Kind code	B2
Filing date	Nov 15, 2017
Priority date	Mar 7, 2017
Publication date	Dec 8, 2020
Grant date	Dec 8, 2020

Abstract

A circuit test method for a test device to test a device under test is provided. The circuit test method includes the steps of applying zero volts to a plurality of power pins of the device under test; applying a test voltage to a first signal pin among a plurality of signal pins of the device under test; and measuring a current on a second signal pin among the plurality of signal pins of the device under test and determining whether there is a leakage current in the device under test.

First claim

What is claimed is:

1. A circuit test method for a test device to test a device under test, comprising:
coupling a plurality of power pins of the device under test to a ground such that all of elements in the device under test are not activated;
when all of the elements in the device under test are not activated, applying a test voltage to a first signal pin among a plurality of signal pins of the device under test;
when all of the elements in the device under test are not activated, measuring a current on a second signal pin among the plurality of signal pins of the device under test, wherein the second signal pin is coupled to the first signal pin; and
determining whether there is a leakage current in the device under test according to the measured current.

2. The circuit test method as claimed in claim 1 , wherein the device under test is an integrated circuit which has been packaged.

3. The circuit test method as claimed in claim 1 , wherein the test voltage is smaller than a predetermined value.

4. The circuit test method as claimed in claim 3 , wherein the predetermined value is 0.6 volts.

5. A circuit test method for a test device to test a device under test, comprising:
applying zero volts to a plurality of power pins of the device under test such that all of elements in the device under test are not activated;
when all of the elements in the device under test are not activated, applying a test voltage to a first signal pin among a plurality of signal pins of the device under test;
when all of the elements in the device under test are not activated, measuring a current on a second signal pin among the plurality of signal pins of the device under test, wherein the second signal pin is coupled to the first signal pin; and
determining whether there is a leakage current in the device under test according to the measured current.

6. The circuit test method as claimed in claim 5 , wherein the device under test is an integrated circuit which has been packaged.

7. The circuit test method as claimed in claim 5 , wherein the test voltage is smaller than a predetermined value.

8. The circuit test method as claimed in claim 7 , wherein the predetermined value is 0.6 volts.

9. A circuit test method for a test device to test a device under test, comprising:
coupling a diode between a first signal pin among a plurality of signal pins of the device under test and a first power pin among a plurality of power pins of the device under test, wherein an anode of the diode is coupled to the first signal pin, and a cathode of the diode is coupled to the first power pin;
when all of elements in the device under test are not activated, applying a test voltage on the first signal pin, wherein the test voltage is lower than a predetermined value so that the diode is not turned on;
when all of the elements in the device under test are not activated, measuring a current on a second signal pin among the plurality of signal pins of the device under test, wherein the second signal pin is coupled to the first signal pin; and
determining whether there is a leakage current in the device under test according to the measured current.

10. The circuit test method as claimed in claim 9 , wherein the device under test comprises a plurality of dies, and all of the pluralty of dies are not activated during the measurement process on the device under test.

11. The circuit test method as claimed in claim 10 , wherein the plurality of power pins are coupled to a ground.

12. The circuit test method as claimed in claim 10 , wherein the plurality of power pins are supplied with zero volts.

13. The circuit test method as claimed in claim 9 , wherein the test voltage is 0.1 volts, 0.4 volts, 0.5 volts or 0.6 volts.

14. The circuit test method as claimed in claim 9 , wherein the device under test is an integrated circuit which has been packaged.

15. The circuit test method as claimed in claim 1 , further comprising:
coupling a diode between the first signal pin and a first power pin among the plurality of power pins, wherein an anode of the diode is coupled to the first signal pin, and a cathode of the diode is coupled to the first power pin,
wherein the test voltage is lower than a predetermined value so that the diode is not turned on.

16. The circuit test method as claimed in claim 5 , further comprising:
coupling a diode between the first signal pin and a first power pin among the plurality of power pins, wherein an anode of the diode is coupled to the first signal pin, and a cathode of the diode is coupled to the first power pin,
wherein the test voltage is lower than a predetermined value so that the diode is not turned on.

17. The circuit test method as claimed in claim 9 , wherein the diode is disposed in the device under test, the anode of the diode is directly connected to the first signal pin, and the cathode of the diode is directly connected to the first power pin.

Assignees

• Silicon Motion Inc

Inventors

• Kuo Hung-Sen
• Chen Te-Wei
• Chang Hung-Sheng
• Kuan Ming-Wan

Classifications

• G01R31/3008

  Quiescent current [IDDQ] test or leakage current test · CPC title

• G01R31/2879

  related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads · CPC title

• G01R31/3177

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/2868 Primary

  Complete testing stations; systems; procedures; software aspects · CPC title

• G01R31/318314

  Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages (simulation software G01R31/318357; emulators G06F11/261) · CPC title