Semiconductor device and multi-chip module

Patent metadata

Field	Value
Publication number	US-9933475-B2
Application number	US-201515535219-A
Country	US
Kind code	B2
Filing date	Apr 24, 2015
Priority date	Apr 24, 2015
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

Provided is a semiconductor inspection circuit which is capable of inspecting connection states of power supply, ground, and signal bumps in a semiconductor package or a printed circuit board equipped with a semiconductor LSI mounted in a product operation state. As a means to solve the problem, a circuit capable of switching a path is provided at an input portion of a driver/receiver, a mechanism capable of transferring an output of a path switching circuit near a receiver circuit to a voltage waveform circuit with an internal variable terminal is provided, and a breakage state of a bump can be observed in the product operation state by observing a DC level at a terminal having a certain DC resistance when a signal bump connection state is observed and receiving a step wave and observing a response waveform thereof when an IO power supply bump connection state is observed.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a first circuit block including first and second output circuits;
a second circuit block including first and second input circuits; and
a wiring block that connects an output pin from the first output circuit and an input pin to the first input circuit via a wiring and connects an output pin from the second output circuit and an input pin to the second input circuit via a wiring,
wherein power supply pins of the first and second circuit blocks configured to supply electric power to the output circuits and the input circuits and a ground pin are connected with a wiring for power supply to the wiring block and a wiring for a ground, and
the second circuit block includes a path switching circuit provided at a stage prior to the input circuits, a resistance switcher provided ahead of a path bifurcated by the path switching circuit, and a voltage observation circuit for observing a voltage between both ends of a resistor of the resistance switcher.

2. The semiconductor device according to claim 1 ,
wherein connection states of the power supply pins are inspected by applying a logic input fixed to high to the first output circuit, applying a logic input of a step wave that switches from low to high to the second output circuit, and observing a power variation waveform bifurcated by the path switching circuit at the stage prior to the first input circuit through the voltage observation circuit.

3. The semiconductor device according to claim 1 ,
wherein a connection state of the ground pin is inspected by applying a logic input fixed to low to the first output circuit, applying a logic input of a step wave that switches from high to low to the second output circuit, and observing a power variation waveform bifurcated by the path switching circuit at the stage prior to the first input circuit through the voltage observation circuit.

4. The semiconductor device according to claim 1 ,
wherein a connection state of a wiring path that connects the output pin from the first output circuit with the input pin to the first input circuit is inspected by applying a logic input which performs transition of low→high→low and has a period of high fixed to a period of time enough to measure a DC resistance (an order of μs) to the first input circuit and by observing a power variation waveform bifurcated by the path switching circuit at the stage prior to the first input circuit through the voltage observation circuit.

5. The semiconductor device according to claim 1 ,
wherein the path switching circuit has a one-input two-output configuration that includes three pass transistors and operates according to a 2-bit control signal.

6. The semiconductor device according to claim 1 ,
wherein the voltage observation circuit includes a multi-step level shift circuit, a multi-step comparator connected to the multi-step level shift circuit, a multi-step FF circuit, and a multi-step shift register.

7. The semiconductor device according to claim 1 ,
wherein the voltage observation circuit includes a level shift circuit, a comparator, and a hold circuit.

8. The semiconductor device according to claim 2 ,
wherein the resistance switcher includes a resistor of a range of 0.1 Ω to 10 Ω and a resistor of 1 kΩ or more, and
a resistance of the resistance switcher is switched to a resistance of 1 kΩ or more.

9. The semiconductor device according to claim 4 ,
wherein the resistance switcher includes a resistor of a range of 0.1 Ω to 10 Ω and a resistor of 1 kΩ or more, and
a resistance of the resistance switcher is switched to a resistance having an appropriate value within a range of 0.1 Ω to 10 Ω.

10. A multi-chip module, comprising:
a first semiconductor LSI including first and second output circuits;
a second semiconductor LSI including first and second input circuits; and
a wiring substrate in which an output pin from the first output circuit is connected with an input pin to the first input circuit via a wiring, and an output pin from the second output circuit is connected with an input pin to the second input circuit via a wiring,
wherein power supply pins of the first and second semiconductor LSIs configured to supply electric power to the output circuits and the input circuits and a ground pin are connected with a wiring for power supply to the wiring substrate and a wiring for a ground, and
the second semiconductor LSI includes a path switching circuit provided at a stage prior to the input circuits, a resistance switcher provided ahead of a path bifurcated by the path switching circuit, and a voltage observation circuit for observing a voltage between both ends of a resistor of the resistance switcher.

11. The multi-chip module according to claim 10 ,
wherein connection states of the power supply pins are inspected by applying a logic input fixed to high to the first output circuit, applying a logic input of a step wave that switches from low to high to the second output circuit, and observing a power variation waveform bifurcated by the path switching circuit at the stage prior to the first input circuit through the voltage observation circuit.

12. The multi-chip module according to claim 10 ,
wherein a connection state of the ground pin is inspected by applying a logic input fixed to low to the first output circuit, applying a logic input of a step wave that switches from high to low to the second output circuit, and observing a power variation waveform bifurcated by the path switching circuit at the stage prior to the first input circuit through the voltage observation circuit.

13. The multi-chip module according to claim 10 ,
wherein a connection state of a wiring path that connects the output pin from the first output circuit with the input pin to the first input circuit is inspected by applying a logic input which performs transition of low→high→low and has a period of high fixed to a period of time enough to measure a DC resistance (an order of μs) to the first input circuit and by observing a power variation waveform bifurcated by the path switching circuit at the stage prior to the first input circuit through the voltage observation circuit.

14. The multi-chip module according to claim 10 ,
wherein the second semiconductor LSI is mounted on the wiring substrate,
the first semiconductor LSI is mounted on the second semiconductor LSI,
the connection between the output pin from the first output circuit and the input pin to the first input circuit and the connection between the output pin from the second output circuit and the input pin to the second input circuit are performed by through silicon vias TSV formed in the second semiconductor LSI instead of the wiring of the wiring substrate, and
the through silicon vias TSV formed in the second semiconductor LSI is used for the connection between the power supply pin of the first semiconductor LSI and the ground pin and the wiring of the wiring substrate.

15. A semiconductor system, comprising:
the semiconductor device according to claim 1 ,
wherein a voltage amount of a normal connection state at a time of device shipment is stored in a memory, and
an abnormal state is determined based on comparison of the voltage amount recorded in the memory and with an actual value at that time.

16. A semiconductor system, comprising:
the semiconductor device according to claim 1 , and
a mechanism that gives an alarm indicating an abnormal position or a state to a system when an abnormality is detected by an inspection circuit.

17. A semiconductor system, co

Assignees

• Hitachi Ltd

Inventors

• Uematsu Yutaka
• Osaka Hideki
• Toba Tadanobu
• Shimbo Kenichi

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/07254

  changes in dispositions · CPC title