High-speed digital-to-analog converter

Patent metadata

Field	Value
Publication number	US-10855306-B2
Application number	US-201916533464-A
Country	US
Kind code	B2
Filing date	Aug 6, 2019
Priority date	Aug 30, 2018
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

A digital-to-analog converter (DAC) capable of operating in radio frequency (RF) with linear output, low distortion, low power consumption, and input data independence. The DAC includes switch drivers and output switches driven by the switch drivers. The switch drivers include pairs of outputs, and positive feedback circuitries coupled between respective pairs of outputs. The output switches are arranged between a first current source configured to push current to the DAC's outputs and a second current source configured to pull current from the DAC's outputs. Different output switches are configured to push current to and pull current from the DAC's outputs in accordance with rising edges and falling edges, respectively.

First claim

What is claimed is:

1. A digital-to-analog converter (DAC) comprising:
first and second switches;
a current source configured to push current to a first output through the first switch based on a first signal and a second output through the second switch based on a second signal; and
a switch driver configured to receive a data signal and a clock signal, the switch driver comprising a latch and a positive feedback circuitry, the latch comprising a first output node for the first signal and a second output node for the second signal, the positive feedback circuitry configured to connect the first output node and the second output node.

2. The DAC of claim 1 , wherein the positive feedback circuitry is configured to receive the clock signal such that the latch can be reset.

3. The DAC of claim 1 , wherein the latch is configured to receive the data signal and the clock signal.

4. The DAC of claim 1 , wherein:
the data signal comprises first and second portions, and
the latch comprises a third output node configured to output a result of an XOR operation of the first and second portions of the data signal.

5. The DAC of claim 1 , wherein:
the latch is configured to receive an inverted version of the clock signal, and
the latch comprises two additional output nodes configured to output based on the inverted version of the clock signal and the first and second signals.

6. The DAC of claim 1 , wherein the switch driver comprises a level shift circuitry configured to shift the voltage levels of the first and second signals such that the first and second switches operate in saturation region.

7. The DAC of claim 1 , wherein:
the latch is a first latch, and
the switch driver comprises a second latch between the first latch and the first and second switches.

8. The DAC of claim 7 , wherein the second latch comprises output nodes that are cross-coupled.

9. The DAC of claim 7 , wherein:
the clock signal is a first clock signal,
the second latch is configured to receive a second clock signal, and
the second clock signal is a delayed version of the first clock signal.

10. The DAC of claim 9 , wherein:
the first latch comprises transistors of a first-type configured to receive the data signal, and
the second latch comprises transistors of a second-type configured to receive the first signal and the second signal.

11. A digital-to-analog converter (DAC) comprising:
a first current source configured to push current to first and second outputs;
a second current source configured to pull current from the first and second outputs; and
a plurality of switch branches configured to, triggered by a first-type edge of a clock signal, push current of the first current source to the first output and pull current of the second current source from the second output, and, triggered by a following second-type edge of the clock signal, push current of the first current source to the second output and pull current of the second current source from the first output.

12. The DAC of claim 11 , wherein:
the plurality of switch branches is a first plurality of switch branches, and
the DAC comprises a second plurality of switch branches comprising dump nodes and configured to steer current to the dump nodes when the first plurality of switch branches would push current to the first and second outputs.

13. The DAC of claim 11 , wherein:
the plurality of switch branches comprise a first switch branch driven by a first signal, and
the first switch branch comprises first and second switches and is configured to, triggered by the first-type edge of the clock signal, push current to or pull current from the first output based on the first signal.

14. The DAC of claim 13 , wherein:
the first switch is coupled between the first current source and the second switch,
the second switch is coupled between the first switch and the second current source, and
the first output is between the first switch and the second switch.

15. The DAC of claim 13 , wherein:
the plurality of switch branches comprise a second switch branch driven by the first signal,
the first signal is coupled to the second switch branch through a latch, and
the second switch branch comprises third and fourth switches and is configured to, triggered by the second-type edge of the clock signal, push current to or pull current from the first output based on the first signal.

16. The DAC of claim 15 , wherein:
the plurality of switch branches comprise a third switch branch driven by a second signal,
the second signal is an inverted version of the first signal, and
the third switch branch comprises fifth and sixth switches and is configured to, triggered by the first-type edge of the clock signal, push current to or pull current from the second output based on the second signal.

17. The DAC of claim 16 , wherein:
the fifth switch is coupled between the first current source and the sixth switch,
the sixth switch is coupled between the fifth switch the second current source, and
the second output is between the fifth switch and the sixth switch.

18. The DAC of claim 16 , wherein:
the plurality of switch branches comprise a fourth switch branch driven by the second signal, and
the fourth switch branch comprises seventh and eighth switches and is configured to, triggered by the second-type edge of the clock signal, push current to or pull current from the second output based on the second signal.

19. The DAC of claim 14 , wherein:
the plurality of switch branches is a first plurality of switch branches,
the DAC comprises a second plurality of switch branches,
the second plurality of switch branches comprise a fifth switch branch driven by a third signal, and
the fifth switch branch is configured to, triggered by the first-type clock edge, throw current away based on the third signal.

20. The DAC of claim 19 , wherein the third signal is a result of an XOR operation of the first signal and the second signal.

Assignees

• Mediatek Singapore Pte Ltd

Inventors

• Egan Nathan

Classifications

• H03M1/0863 Primary

  of switching transients, e.g. glitches · CPC title

• H03M1/76 Primary

  using switching tree · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/326

  by averaging out the errors · CPC title

• H03M3/324

  characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement · CPC title