Semiconductor device

US10855196B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10855196-B2
Application numberUS-201916536921-A
CountryUS
Kind codeB2
Filing dateAug 9, 2019
Priority dateMar 18, 2019
Publication dateDec 1, 2020
Grant dateDec 1, 2020

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device including a main board; a first board provided on the main board; first and second semiconductor elements provided on the first board; a first positive terminal provided on the first board; a first negative terminal provided on the first board; a first output terminal provided on the first board; a second board provided on the main board; third and fourth semiconductor elements provided on the second board; a second positive terminal provided on the second board; a second negative terminal provided on the second board; a second output terminal provided on the second board; a first terminal plate connecting the first positive terminal and the second positive terminal, a second terminal plate connecting the first negative terminal and the second negative terminal, and a third terminal plate connecting the first output terminal and the second output terminal.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a main board; a first board provided on the main board; a first semiconductor element provided on the first board; a second semiconductor element provided on the first board; a first positive terminal provided on the first board; a first negative terminal provided on the first board; a first output terminal provided on the first board; a second board provided on the main board; a third semiconductor element provided on the second board; a fourth semiconductor element provided on the second board; a second positive terminal provided on the second board; a second negative terminal provided on the second board; a second output terminal provided on the second board; and at least one terminal plate of a first terminal plate connecting the first positive terminal and the second positive terminal, a second terminal plate connecting the first negative terminal and the second negative terminal, and a third terminal plate connecting the first output terminal and the second output terminal. 2. The semiconductor device according to claim 1 , further comprising: a first electrode member having the first positive terminal; a second electrode member having the first output terminal; a third electrode member having the second positive terminal; and a fourth electrode member having the second output terminal, wherein the first semiconductor element is provided on the first electrode member, the second semiconductor element is provided on the second electrode member, the third semiconductor element is provided on the third electrode member, and the fourth semiconductor elements is provided on the fourth electrode member. 3. The semiconductor device according to claim 2 , further comprising: a fifth electrode member having the first negative terminal; and a sixth electrode member having the second negative terminal. 4. The semiconductor device according to claim 3 , wherein the first electrode member and the third electrode member are provided at positions facing each other, wherein the second electrode member and the fourth electrode member are provided at positions facing each other, and wherein the fifth electrode member and the sixth electrode member are provided at positions facing each other. 5. The semiconductor device according to claim 3 , further comprising a second wire connecting the fifth electrode member and the sixth electrode member. 6. The semiconductor device according to claim 2 , further comprising: a third board provided on the main board; a seventh electrode member provided on the third board and having a third negative terminal; a fourth board provided on the main board; and an eighth electrode member provided on the fourth board and having a fourth negative terminal, wherein the second terminal plate includes: a first plate portion; a first wiring portion having one end connected to the first plate portion and the other end connected to the first negative terminal; a second wiring portion having one end connected to the first plate portion and the other end connected to the second negative terminal; a third wiring portion having one end connected to the first plate portion and the other end connected to the third negative terminal; and a fourth wiring portion having one end connected to the first plate portion and the other end connected to the fourth negative terminal. 7. The semiconductor device according to claim 6 , further comprising: a ninth electrode member provided on the third board and having a third output terminal; and a tenth electrode member provided on the fourth board and having a fourth output terminal, wherein the third terminal plate includes: a second plate portion; a fifth wiring portion having one end connected to the second plate portion and the other end connected to the first output terminal; a sixth wiring portion having one end connected to the second plate portion and the other end connected to the second output terminal; a seventh wiring portion having one end connected to the second plate portion and the other end connected to the third output terminal; and an eighth wiring portion having one end connected to the second plate portion and the other end connected to the fourth output terminal. 8. The semiconductor device according to claim 7 , further comprising: an eleventh electrode member provided on the third board and having a third positive terminal; a twelfth electrode member provided on the fourth board and having a fourth positive terminal; a fifth semiconductor element provided on the eleventh electrode member; a sixth semiconductor element provided on the ninth electrode member and electrically connected in series to the fifth semiconductor element; a seventh semiconductor element provided on the twelfth electrode member; and an eighth semiconductor element provided on the tenth electrode member and electrically connected in series to the seventh semiconductor element. 9. The semiconductor device according to claim 8 , wherein the first terminal plate further connects the third positive terminal and the fourth positive terminal. 10. The semiconductor device according to claim 8 , further comprising a fourth wire connecting the first electrode member and the eleventh electrode member. 11. The semiconductor device according to claim 7 , further comprising a fifth wire connecting the second electrode member and the ninth electrode member. 12. The semiconductor device according to claim 2 , further comprising a first wire connecting the second electrode member and the fourth electrode member. 13. The semiconductor device according to claim 2 , further comprising a third wire connecting the first electrode member and the third electrode member. 14. The semiconductor device according to claim 1 , wherein the first semiconductor element and the second semiconductor element are electrically connected in series, and wherein the third semiconductor element and the fourth semiconductor element are electrically connected in series.

Assignees

Inventors

Classifications

  • for devices provided for in groups H10D8/00 - H10D48/00 · CPC title

  • between laterally-adjacent chips · CPC title

  • Bond wires · CPC title

  • specially adapted for the configuration of power bus bars · CPC title

  • Die-attach connectors and bond wires · CPC title

Patent family

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External sources

Frequently asked questions

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What does patent US10855196B2 cover?
A semiconductor device including a main board; a first board provided on the main board; first and second semiconductor elements provided on the first board; a first positive terminal provided on the first board; a first negative terminal provided on the first board; a first output terminal provided on the first board; a second board provided on the main board; third and fourth semiconductor el…
Who is the assignee on this patent?
Toshiba Kk, Toshiba Electronic Devices & Storage Corp
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 01 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).