Semiconductor device including dielectric structure having ferroelectric layer and non-ferroelectric layer

Patent metadata

Field	Value
Publication number	US-10854707-B2
Application number	US-201916536044-A
Country	US
Kind code	B2
Filing date	Aug 8, 2019
Priority date	Dec 27, 2018
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

A semiconductor device according to an embodiment includes a first electrode, a dielectric layer structure disposed on the first electrode and having a ferroelectric layer and a non-ferroelectric layer, and a second electrode disposed on the dielectric structure. The ferroelectric layer has positive and negative coercive electric fields having different absolute values. The dielectric structure has a non-ferroelectric property.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first electrode;
a dielectric structure disposed on the first electrode and having a ferroelectric layer and a non-ferroelectric layer; and
a second electrode disposed on the dielectric structure,
wherein the ferroelectric layer has positive and negative coercive electric fields having different absolute values, and,
wherein the dielectric structure has a non-ferroelectric property.

2. The semiconductor device of claim 1 ,
wherein the non-ferroelectric layer has a paraelectric property.

3. The semiconductor device of claim 1 ,
wherein the absolute value of the positive coercive electric field is less than the absolute value of the negative coercive electric field.

4. The semiconductor device of claim 1 ,
wherein the ferroelectric layer comprises at least one selected from the group consisting of hafnium oxide, zirconium oxide and hafnium zirconium oxide.

5. The semiconductor device of claim 1 ,
wherein the non-ferroelectric layer comprises at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide and hafnium zirconium oxide.

6. The semiconductor device of claim 1 ,
wherein the non-ferroelectric layer and the ferroelectric layer are sequentially stacked between the first electrode and the second electrode.

7. The semiconductor device of claim 1 ,
wherein the ferroelectric layer comprises a first region adjacent to the second electrode and a second region outside the first region,
wherein the second region is distal the second electrode and proximal the first region, and
wherein a concentration of oxygen vacancy of the first region is higher than a concentration of oxygen vacancy of the second region.

8. The semiconductor device of claim 7 ,
wherein the first region has a concentration gradient of oxygen vacancy.

9. The semiconductor device of claim 1 ,
wherein the ferroelectric layer comprises a dopant,
wherein the ferroelectric layer comprises a first region having a relatively high concentration of the dopant and a second region having a relatively low concentration of the dopant, and
wherein the first region has a concentration gradient of the dopant.

10. A semiconductor device comprising:
a substrate having a channel region;
a gate dielectric structure disposed on the channel region and including a ferroelectric layer and a non-ferroelectric layer; and
a gate electrode layer disposed on the gate dielectric structure,
wherein the ferroelectric layer has a positive and a negative coercive electric field having different absolute values, and
wherein the gate dielectric structure has a non-ferroelectric property.

11. The semiconductor device of claim 10 ,
wherein the non-ferroelectric layer has a paraelectric property.

12. The semiconductor device of claim 10 ,
wherein the absolute value of the positive coercive electric field is less than the absolute value of the negative coercive electric field.

13. The semiconductor device of claim 10 ,
wherein the ferroelectric layer comprises at least one selected from the group consisting of ferroelectric hafnium oxide, ferroelectric zirconium oxide, and ferroelectric hafnium zirconium oxide.

14. The semiconductor device of claim 10 ,
wherein the non-ferroelectric layer comprises at least one selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, paraelectric hafnium oxide, paraelectric zirconium oxide, and paraelectric hafnium zirconium oxide.

15. The semiconductor device of claim 10 ,
wherein the non-ferroelectric layer is disposed on the channel region, and
wherein the ferroelectric layer is disposed on the non-ferroelectric layer.

16. The semiconductor device of claim 10 ,
wherein the ferroelectric layer comprises a first region disposed in an inner region adjacent to the second electrode, and a second region outside the first region,
wherein the second region is distal the second electrode and proximal the first region, and
wherein a concentration of oxygen vacancy of the first region is higher than a concentration of oxygen vacancy of the second region.

17. The semiconductor device of claim 16 ,
wherein the first region has a concentration gradient of oxygen vacancy.

18. The semiconductor device of claim 10 ,
wherein the ferroelectric layer comprises a dopant,
wherein the ferroelectric layer comprises a first region having a relatively high concentration of the dopant and a second region having a relatively low concentration of the dopant, and
wherein the first region has a concentration gradient of the dopant.

19. A semiconductor device comprising:
a gate dielectric structure disposed on a channel region of a substrate of the device, the gate dielectric structure including a ferroelectric layer and a non-ferroelectric layer; and
wherein the ferroelectric layer has a first region and a first region thickness generated by a first region concentration gradient of oxygen vacancies which trap negative charge and polarize a corresponding positive charge and generate an internal electric field,
wherein the gate dielectric structure has a paraelectric property and a controlled capacitance by a capacitance matching of the ferroelectric layer and the non-ferroelectric layer.

20. The semiconductor device of claim 19 ,
wherein the ferroelectric layer further has a suppressed ferroelectric polarization characteristic through the capacitance matching to suppress a leakage current passing through the gate dielectric structure.

Assignees

• Sk Hynix Inc

Inventors

• Yoo Hyangkeun
• Lee Se Ho
• Lee Jae Gil

Classifications

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D64/689 Primary

  having ferroelectric layers · CPC title

• H10D64/311

  Gate electrodes for field-effect devices · CPC title

• H10D64/033 Primary

  comprising ferroelectric layers · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title