Integrated enhancement mode and depletion mode device structure and method of making the same

Patent metadata

Field	Value
Publication number	US-10854600-B2
Application number	US-201916577629-A
Country	US
Kind code	B2
Filing date	Sep 20, 2019
Priority date	Oct 8, 2014
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

A method of forming an integrated circuit can include forming a heterostructure over a substrate structure, wherein the given substrate structure comprises a given semiconductor material. The method can include etching a castellated channel region in an e-mode device area of the heterostructure that defines a plurality of ridge channels interleaved between a plurality of trenches, the ridge channels comprising another semiconductor material. The method can also include forming an isolation region on the heterostructure to electrically isolate the e-mode device area from a d-mode device area of the heterostructure. The method can further include forming a mask with an opening that defines a castellated gate opening overlying the castellated channel region and the mask defines an opening overlaying a single planar gate overlying the d-mode device area of the heterostructure. The method can also include performing a contact fill with conductive material to form a castellated gate contact.

First claim

What is claimed is:

1. A method of forming an integrated circuit comprising:
forming a heterostructure over a substrate structure;
forming an isolation region on the heterostructure to electrically isolate an e-mode device area from a d-mode device area of the heterostructure;
etching a castellated channel region in the e-mode device area of the heterostructure to define a plurality of ridge channels interleaved between a plurality of trenches, wherein each trench of the plurality of trenches exposes a top planar semiconductor surface of the substrate structure between neighboring ridge channels of the plurality of ridge channels;
depositing a mask over the castellated channel region in the e-mode device area and a single planar gate region in the d-mode device area of the heterostructure;
etching the mask to provide a castellated gate opening in the the castellated channel region, wherein the etching of the mask further provides a planar gate opening in the single planar gate region; and
performing a contact fill with a conductive material of the castellated gate opening to form a castellated gate contact that extends across the castellated channel region and substantially surrounds each of the plurality of ridge channels around their top and their sides to overlap a channel interface of the heterostructure of each of the plurality of ridge channels, such that the castellated gate contact extends along at least a portion of a length of each ridge channel.

2. The method of claim 1 , wherein the performing a contact fill to form a castellated gate contact further comprises performing a contact fill with the conductive material of the planar gate opening to form the d-mode device.

3. The method of claim 2 , further comprising:
depositing and patterning a photoresist material layer over the heterostructure to provide trench openings over the castellated channel region of the e-mode device area;
depositing a mask material to fill the trench openings; and
lifting off a portion of the mask material and removing the patterned photoresist material layer to leave the mask material where the trench openings where formed.

4. The method of claim 3 , wherein the mask is a first mask and the method further comprising:
forming a second mask;
depositing and patterning a second photoresist material layer over the heterostructure to cover the castellated channel region of the e-mode device area;
depositing a mask material to cover the remaining top surface of heterostructure; and
lifting off a portion of the mask material and removing the second patterned photoresist material layer to expand the second mask to cover the remaining top surface of the heterostructure.

5. The method of claim 4 , wherein the second mask is formed from nickel (Ni).

6. The method of claim 1 , wherein the mask is formed from silicon nitride (Si 3 N 4 ).

7. The method of claim 1 , wherein the etching of the mask to provide the castellated channel region in the e-mode device area of the heterostructure comprises etching with an inductively coupled plasma (ICP) etcher to form the castellated channel region.

8. The method of claim 1 , wherein the heterostructure comprises an aluminum gallium nitride (AlGaN) layer overlying a gallium nitride layer (GaN).

Assignees

• Parke Justin Andrew
• Stewart Eric J
• Howell Robert S
• Henry Howell George
• Nechay Bettina
• Cramer Harlan Carl
• King Matthew Russell
• Gupta Shalini
• Freitag Ronald G
• Renaldo Karen Marie
• Northrop Grumman Systems Corp

Inventors

• Parke Justin Andrew
• Stewart Eric J
• Howell Robert S
• Henry Howell George
• Nechay Bettina
• Cramer Harlan Carl
• King Matthew Russell
• Gupta Shalini
• Freitag Ronald G
• Renaldo Karen Marie

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/117

  Shapes of semiconductor bodies · CPC title

• H10D84/05

  using Group III-V technology · CPC title