Uniaxially-strained FD-SOI finFET

Patent metadata

Field	Value
Publication number	US-9252208-B1
Application number	US-201414447678-A
Country	US
Kind code	B1
Filing date	Jul 31, 2014
Priority date	Jul 31, 2014
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

First claim

What is claimed is:

1. A transistor comprising:
an insulating layer formed on a substrate;
a plurality of nanoscale, uniaxially-strained semiconductor bars arranged in a horizontal array on the insulating layer, the bars spaced apart from one another by a spacing that is less than 30 nm; and
a single and contiguous gate extending over the horizontal array.

2. The transistor of claim 1 , wherein a width of the semiconductor bars is greater than the spacing between the bars.

3. The transistor of claim 1 , wherein the spacing between the bars is less than 10 nm.

4. The transistor of claim 1 , wherein the nanoscale strained semiconductor bars have uniaxial strain ratios greater than 10:1.

5. The transistor of claim 1 , wherein the nanoscale, strained semiconductor bars have uniaxial strain ratios greater than 50:1.

6. The transistor of claim 1 , further comprising a plurality of channel regions under the gate formed from a first portion of the horizontal array.

7. The transistor of claim 6 , wherein the channel regions are fully depleted.

8. The transistor of claim 7 , wherein the insulating layer is an ultra-thin buried oxide having a thickness less than 25 nm.

9. The transistor of claim 6 , wherein the transistor is a FD-SOI transistor having an ultra-thin body and buried oxide layer.

10. The transistor of claim 1 , wherein a width of each bar of the plurality of nanoscale, strained semiconductor bars is between approximately 10 nm and approximately 200 nm and a height of each bar is less than approximately 20 nm.

11. The transistor of claim 1 , wherein the semiconductor bars are formed from one or more of silicon, SiGe or SiC, GaAs, GaN, InP, InAGaAs, InGaN, or combinations thereof.

12. The transistor of claim 1 , further comprising source merging material formed at a source region, wherein the source region comprises first portions of the plurality of nanoscale, strained semiconductor bars and the source merging material electrically connects the first portions.

13. The transistor of claim 12 , wherein the source merging material comprises an epitaxially-grown semiconductor material grown from the first portions of the horizontal array.

14. The transistor of claim 12 , further comprising drain merging material formed at a drain region, wherein the drain region comprises second portions of the plurality of nanoscale, strained semiconductor bars and the drain merging material electrically connects the second portions.

15. The transistor of claim 1 formed in a memory circuit.

16. The transistor of claim 1 formed in a microprocessor circuit.

17. A transistor array, comprising:
a substrate having a buried oxide layer;
a plurality of nanoscale uniaxially-strained semiconductor bars arranged in a horizontal array on the buried oxide layer, the bars spaced apart from one another by a spacing distance that is less than 30 nm;
source regions formed from first portions of the semiconductor bars, the source regions coupled to one another by a source merging material;
drain regions formed from second portions of the semiconductor bars, the drain regions coupled to one another by a drain merging material; and
a single and contiguous gate extending over the horizontal array.

18. The transistor array of claim 17 wherein the source merging material and the drain merging material are epitaxially grown.

19. The transistor array of claim 17 wherein the source regions and the drain regions are doped with ions.

20. The transistor array of claim 17 wherein portions of the semiconductor bars underneath the gate are doped channel regions having a polarity opposite that of the source and drain regions.

Assignees

• St Microelectronics Inc
• Commissariat à l'énergie atomique et aux énergies alternatives
• Globalfoundries Inc
• Commissariat Energie Atomique

Inventors

• Morin Pierre
• Vinet Maud
• Grenouillet Laurent
• Jacob Ajey Poovannummoottil

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P14/61

  using masks · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title