Displays with data lines that accommodate openings

Patent metadata

Field	Value
Publication number	US-10852607-B2
Application number	US-201916505532-A
Country	US
Kind code	B2
Filing date	Jul 8, 2019
Priority date	Aug 21, 2018
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

To minimize the width of a non-light-emitting border region around an opening in the active area, data lines may be stacked in the border region. Data line portions may be formed using three metal layers in three different planes within the border region. A metal layer that forms a positive power signal distribution path in the active area may serve as a data line portion in the border region. A metal layer may be added in the border region to serve as a data line portion in the border region. Data line signals may also be provided to pixels on both sides of an opening in the active area using supplemental data line paths. A supplemental data line path may be routed through the active area of the display to electrically connect data line segments on opposing sides of an opening within the display.

First claim

What is claimed is:

1. A display comprising:
a substrate having an active area that includes an array of pixels and an opening within the active area, wherein the opening has first and second opposing sides and is surrounded by a border region;
a plurality of gate lines coupled to the array of pixels;
a plurality of data lines coupled to the array of pixels, wherein a subset of the plurality of data lines are rerouted within the border region from the first side to the second side and wherein the subset of the plurality of data lines has portions in the border region that are formed from a first metal layer that is formed in a first plane, a second metal layer that is formed in a second plane that is lower than the first plane, and a third metal layer that is formed in a third plane that is lower than the second plane;
a first conductive via that electrically connects the third metal layer to a first portion of the second metal layer; and
a second conductive via that electrically connects the first metal layer to a second portion of the second metal layer.

2. The display defined in claim 1 , wherein the plurality of gate lines are at least partially formed from a fourth metal layer that is formed in a fourth plane that is interposed between the second and third planes.

3. The display defined in claim 2 , wherein the plurality of gate lines are at least partially formed from a fifth metal layer that is formed in a fifth plane that is different than the fourth plane and interposed between the second and third planes.

4. The display defined in claim 1 , further comprising:
at least a first dielectric layer interposed between the first metal layer and the second metal layer; and
at least a second dielectric layer interposed between the second metal layer and the third metal layer.

5. The display defined in claim 4 , wherein the at least first dielectric layer comprises an organic planarization layer and an inorganic passivation layer.

6. The display defined in claim 4 , wherein the at least second dielectric layer comprises an interlayer dielectric layer and a gate insulator layer.

7. The display defined in claim 4 , further comprising:
a buffer layer interposed between the third metal layer and the substrate.

8. The display defined in claim 1 , further comprising:
an inorganic buffer layer formed on the substrate; and
a gate insulator layer formed on the inorganic buffer layer, wherein the third metal layer is interposed between the gate insulator layer and the inorganic buffer layer.

9. The display defined in claim 8 , further comprising:
first and second interlayer dielectric layers;
a fourth metal layer covered by the first interlayer dielectric layer; and
a fifth metal layer covered by the second interlayer dielectric layer.

10. The display defined in claim 9 , further comprising:
an inorganic passivation layer formed on the second interlayer dielectric layer, wherein the second metal layer is interposed between the inorganic passivation layer and the second interlayer dielectric layer;
a first organic planarization layer formed on the inorganic passivation layer; and
a second organic planarization layer formed on the first organic planarization layer, wherein the third metal layer is interposed between the first and second organic planarization layers.

11. A display comprising:
a substrate having an active area that includes an array of pixels and an opening within the active area, wherein the opening has first and second opposing sides and is surrounded by a border region;
a plurality of gate lines coupled to the array of pixels; and
a plurality of data lines coupled to the array of pixels, wherein a subset of the plurality of data lines are rerouted within the border region from the first side to the second side, wherein the subset of the plurality of data lines has portions in the border region that are formed from a first metal layer that is formed in a first plane, a second metal layer that is formed in a second plane that is lower than the first plane, and a third metal layer that is formed in a third plane that is lower than the second plane, wherein the first metal layer has a first portion formed in the border region and a second portion formed in the active area that is not electrically connected to the first portion, wherein the first portion of the first metal layer forms some of the subset of the plurality of data lines, and wherein the second portion of the first metal layer forms a positive power supply distribution line.

12. The display defined in claim 11 , wherein the second metal layer has a first portion formed in the border region and a second portion formed in the active area, wherein the first portion of the second metal layer forms some of the subset of the plurality of data lines, and wherein the second portion of the second metal layer forms portions of the plurality of data lines that are in the active area.

13. The display defined in claim 12 , wherein the third metal layer is not present in the active area.

14. A display comprising:
a substrate having an active area that includes an array of pixels, an inactive area that surrounds the active area, and an opening within the active area, wherein the opening has first and second opposing sides;
a plurality of gate lines coupled to the array of pixels; and
a plurality of data lines coupled to the array of pixels, wherein a first portion of the plurality of data lines are uninterrupted by the opening and a second portion of the plurality of data lines are interrupted by the opening, wherein each data line in the second portion of the plurality of data lines has a first data line segment on the first side of the opening, a second data line segment on the second side of the opening, and a supplemental data line path that is routed through the active area and that is electrically connected to the first data line segment and the second data line segment, and wherein each supplemental data line path is electrically connected to a respective first data line segment in the inactive area.

15. The display defined in claim 14 , wherein the inactive area has first and second opposing sides, wherein each supplemental data line path is electrically connected to the respective first data line segment on the first side of the inactive area, and wherein each supplemental data line path is electrically connected to a respective second data line segment on the second side of the inactive area.

16. The display defined in claim 14 , wherein each supplemental data line path is electrically connected to a respective second data line segment in the inactive area.

17. The display defined in claim 14 , wherein each supplemental data line path is electrically connected to a respective second data line segment in the active area.

18. The display defined in claim 14 , wherein each supplemental data line path is at least partially formed by a first metal layer and wherein the first metal layer is interposed between second and third metal layers that form a positive power supply distribution line.

19. The display defined in claim 14 , wherein a first supplemental data line path of the supplemental data line paths has a horizontal portion that is formed from a first metal layer that is routed above an emission line that carries an emission enable control signal, wherein the first supplemental data line path has a vertical portion that is electrically connected to the horizontal portion, and wherein the vertical portion is formed from a second metal layer that is routed

Assignees

• Apple Inc

Inventors

• Yeh Shin-Hung
• Rieutort-Louis Warren S
• Jamshidi Roudbari Abbas
• Lee Chien-Ya
• Tsai Lun

Classifications

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2310/0262

  The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title