Liquid crystal display panel

US10095078B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10095078-B2
Application numberUS-201615144178-A
CountryUS
Kind codeB2
Filing dateMay 2, 2016
Priority dateJan 21, 2013
Publication dateOct 9, 2018
Grant dateOct 9, 2018

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

According to an aspect, a liquid crystal display panel includes an extending portion. The extending portion is metal wiring provided on the same plane as a plane parallel to a surface of a TFT substrate on which a scan line extends in the X-direction, and is electrically conductive metal extending from the scan line. The extending portion partially overlaps a space, but does not overlap an opening area, in the Z-direction.

First claim

Opening claim text (preview).

The invention is claimed as follows: 1. A liquid crystal display panel comprising: a first substrate; a second substrate disposed so as to face the first substrate; and a liquid crystal layer interposed between the first and the second substrates, wherein the first substrate includes a plurality of pixel units arranged in a matrix, each of the pixel units comprising: a pixel electrode; a thin-film transistor that includes a semiconductor layer that is substantially U-shaped in a plan view, the thin-film transistor being coupled to the pixel electrode at a first coupling portion; a first metal wiring line that extends in a first direction and that lies in a layer different from the semiconductor layer in a vertical direction that is orthogonal to a surface of the first substrate; a second metal wiring line that extends in a second direction different from the first direction so as to three-dimensionally cross the first metal wiring line, the second metal wiring line being coupled to the semiconductor layer at a second coupling portion; a pedestal that is quadrangular in a plan view and that is disposed at the first coupling portion in a plane same as a plane of the second metal wiring line; and an extending portion that is a part of the first metal wiring line and that protrudes from the first metal wiring line, the extending portion extending along the second metal wiring line, wherein: in the first direction that is along a shorter side of each pixel unit, the extending portion is adjacent to the pedestal; and in the second direction that is along a longer side of each pixel unit, a length of the extending portion is smaller than a length of the pedestal. 2. The liquid crystal display panel according to claim 1 , the extending portion includes two extending regions, each of the extending regions is arranged between the pedestal and second metal wiring line adjacent to the pedestal, and in the first direction, a space between the second metal wiring line and each of the extending regions is smaller than a space between each of the extending regions and the pedestal. 3. The liquid crystal display panel according to claim 1 , wherein the extending portion partially overlaps with the second metal wiring line. 4. The liquid crystal display panel according to claim 1 , wherein the semiconductor layer is disposed in a plane between a plane of the first metal wiring line and a plane of the second metal wiring line in the vertical direction. 5. The liquid crystal display panel according to claim 1 , wherein the first metal wiring line three-dimensionally crosses the semiconductor layer at two portions. 6. The liquid crystal display panel according to claim 1 , wherein the extending portion has an electric potential that is the same as an electric potential of the first metal wiring line. 7. The liquid crystal display panel according to claim 5 , wherein the thin-film transistor is a double-gate transistor including a first channel and a second channel, and the first and the second channels extend parallel to each other. 8. A liquid crystal display panel comprising: a first substrate; a second substrate disposed so as to face the first substrate; and a liquid crystal layer interposed between the first and the second substrates, wherein the first substrate includes: a plurality of pixel electrodes arranged in a matrix; a plurality of thin-film transistors, each of which includes a semiconductor layer that is substantially U-shaped in a plan view and, the thin-film transistors being coupled to the pixel electrodes; a plurality of scan lines, each of which extends in a first direction and lies in a layer different from the semiconductor layer in a vertical direction that is orthogonal to a surface of the first substrate, the scan lines being disposed at both ends of respective pixel electrode so as to three-dimensionally cross some parts of the semiconductor layer; a plurality of signal lines which extend in a second direction different from the first direction and three-dimensionally cross the scan lines, the signal lines being disposed at both sides of respective pixel electrode; a plurality of pedestal having a quadrangular shape and disposed at a coupling portion, the pedestals being made of a same metal as the signal line; and extending portions, each of which is a part of a corresponding scan line and protrudes from the corresponding scan line, the extending portions extending along the signal lines, wherein: a plurality of pixel areas are defined by the scan lines and the signal lines and arranged in a matrix; in the first direction that is along a shorter side of each pixel area, two extending portions are adjacent to a corresponding pedestal and disposed between two signal lines, and a distance between the extending portions that are between the two signal lines is larger than a distance between pedestals and extending portions adjacent to each other; and in the second direction that is along a longer side of each pixel area, a length of the extending portion is smaller than a length of the pedestal. 9. The liquid crystal display panel according to claim 8 , wherein the second substrate includes a color filter layer disposed so as to face the pixel electrodes, and the extending portions are disposed without overlapping opening areas in which the color filter layer overlaps the pixel electrodes in the vertical direction. 10. The liquid crystal display panel according to claim 9 , wherein each of the thin-film transistors includes a semiconductor layer that is substantially U-shaped in a plan view, and each of the thin-film transistors is a double-gate transistor including: a first channel that is formed in the semiconductor layer at one of intersections of the scan lines and the signal lines; and a second channel that is formed in the semiconductor layer above the scan lines and between the two signal lines, and the first and the second channels extend parallel to each other. 11. The liquid crystal display panel according to claim 10 , wherein the semiconductor layer is disposed in a plane between a plane of the scan lines and a plane of the signal lines in the vertical direction. 12. A liquid crystal display panel comprising: a first substrate; a second substrate disposed so as to face the first substrate; and a liquid crystal layer interposed between the first and the second substrates, wherein the first substrate includes: a plurality of pixel electrodes arranged in a matrix; a plurality of thin-film transistors, each of which is coupled to the pixel electrodes at a first coupling portion; a plurality of first metal wiring lines, each of which extends in a first direction and lies in a layer different from a semiconductor layer of the thin-film transistors in a vertical direction that is orthogonal to a surface of the first substrate, the first metal wiring being three-dimensionally crosses some parts of the semiconductor layer; a plurality of second metal wiring lines, each of which extends in a second direction different from the first direction so as to three-dimensionally cross the first metal wiring lines, the second metal wiring lines being coupled to a second coupling portion of each of the thin-film transistors; a plurality of pedestals, each of which is disposed between adjacent second metal wiring lines and coupled to the first coupling portion, the pedestals being made of a same metal as the second metal wiring lines; a plurality of extending portions, each of which is a part of the respective first metal wiring line and which is protruding from a corresponding first metal wiring line, the extending portio

Assignees

Inventors

Classifications

  • Wiring, e.g. gate line, drain line · CPC title

  • Colour filters · CPC title

  • in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

  • Matrix · CPC title

  • Arrangements for improving the aperture ratio · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10095078B2 cover?
According to an aspect, a liquid crystal display panel includes an extending portion. The extending portion is metal wiring provided on the same plane as a plane parallel to a surface of a TFT substrate on which a scan line extends in the X-direction, and is electrically conductive metal extending from the scan line. The extending portion partially overlaps a space, but does not overlap an open…
Who is the assignee on this patent?
Japan Display Inc
What technology area does this patent fall under?
Primary CPC classification G02F1/136286. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 09 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).