Display circuitry with reduced metal routing resistance

Patent metadata

Field	Value
Publication number	US-9704888-B2
Application number	US-201414150458-A
Country	US
Kind code	B2
Filing date	Jan 8, 2014
Priority date	Jan 8, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A display may have a color filter layer and a thin-film transistor layer. A layer of liquid crystal material may be located between the color filter layer and the thin-film transistor (TFT) layer. The TFT layer may include thin-film transistors formed on top of a glass substrate. A passivation layer may be formed on the thin-film transistor layers. An oxide liner may be formed on the passivation layer. A first low-k dielectric layer may be formed on the oxide liner. A second low-k dielectric layer may be formed on the first low-k dielectric layer. A common voltage electrode and associated storage capacitance may be formed on the second low-k dielectric layer. Thin-film transistor gate structures may be formed in the passivation layer. Conductive routing structures may be formed on the oxide liner, on the first low-k dielectric layer, and on the second low-k dielectric layer. The use of routing structures on the oxide liner reduces overall routing resistance and enables interlaced metal routing, which can help reduce the inactive border area outside the active display regions.

First claim

What is claimed is:

1. Display circuitry that forms an active area of a display having an array of display pixels that display images to a user and that forms an inactive area of the display that surrounds the active area, the display circuitry comprising:
a substrate;
a thin-film transistor formed over the substrate in the active area;
a gate insulator layer formed over the substrate;
a passivation layer formed on the thin-film transistor, wherein a gate electrode of the thin-film transistor is interposed between the passivation layer and the gate insulator layer;
a first dielectric layer formed on the passivation layer;
a second dielectric layer formed on the first dielectric layer;
a first metal layer that forms conductive routing structures in the inactive area, wherein the first metal layer is interposed between the first dielectric layer and the second dielectric layer and wherein the conductive routing structures in the inactive area couple a display driver circuit in the inactive area to control lines in the active area that control the display pixels;
a dielectric planarization layer formed on the second dielectric layer;
a second metal layer that forms conductive routing structures in the inactive area interposed between the second dielectric layer and the dielectric planarization layer;
a third metal layer that forms conductive routing structures in the inactive area formed on the dielectric planarization layer;
a layer of insulating material in the active area and in the inactive area, wherein the third metal layer is interposed between the layer of insulating material and the dielectric planarization layer in the active area and in the inactive area; and
a pixel electrode in the active area, wherein the layer of insulating material and the third metal layer are interposed between the pixel electrode and the substrate in the active area.

2. The display circuitry defined in claim 1 , wherein the passivation layer comprises silicon nitride.

3. The display circuitry defined in claim 1 , wherein the first dielectric layer comprises etch-stop material.

4. The display circuitry defined in claim 1 , wherein the second dielectric layer comprises low-k dielectric material.

5. The display circuitry defined in claim 1 , wherein the first metal layer and the second metal layer exhibit substantially similar resistivity.

6. The display circuitry defined in claim 1 , wherein the gate electrode is formed from conductive material exhibiting greater sheet resistance than that of the first and second metal layers.

7. The display circuitry defined in claim 6 , wherein the gate electrode is formed in the passivation layer.

8. Electronic device display structures that form an active area and an inactive area in a display, comprising:
a substrate;
a layer of liquid crystal material;
a pixel electrode that applies an electric field to the layer of liquid crystal material;
a thin-film transistor formed over the substrate in the active area, wherein the thin-film transistor is coupled to the pixel electrode and controls the electric field, and wherein the thin-film transistor comprises:
source-drain structures formed over the substrate;
a first gate structure formed over the source-drain structures; and
a second gate structure formed over the first gate structure;

a passivation layer formed on the first gate structure;
a first dielectric layer formed on the passivation layer, wherein the passivation layer and the first dielectric layer are interposed between the first and second gate structures; and
a first metal layer, wherein the first metal layer forms conductive routing structures in the inactive area, wherein the first metal layer forms the second gate structure, wherein the first metal layer is formed on the first dielectric layer, and wherein the conductive routing structures couple a display driver circuit in the inactive area to control lines in the active area.

9. The electronic device display structures defined in claim 8 , wherein the first gate structure is formed from a first material and wherein the second gate structure is formed from a second material that is different than the first material.

10. The electronic device display structures defined in claim 9 , wherein the first material exhibits a sheet resistance that is greater than that of the second material.

11. The electronic device display structures defined in claim 8 , further comprising:
a first gate line that is coupled to the first gate structure; and
a second gate line that is coupled to the second gate structure, wherein the first gate line is orthogonal to the second gate line.

12. A display with an active area and an inactive area, comprising:
a substrate;
a thin-film transistor on the substrate in the active area, wherein the thin-film transistor includes a layer of active semiconductor material and a gate electrode formed from a first metal layer;
a data line formed from a second metal layer that is electrically coupled to the layer of active semiconductor material at a source-drain terminal of the thin-film transistor;
a layer of dielectric material interposed between the first metal layer and the second metal layer;
a third metal layer that is formed on the layer of dielectric material and interposed between the first metal layer and the second metal layer, wherein the third metal layer forms a conductive routing structure in the inactive area that couples the data line to a display driver; and
a layer of transparent conductive material that overlaps and is shorted to the second metal layer, wherein the layer of transparent conductive material forms a pixel electrode in the active area.

13. The display defined in claim 12 , further comprising:
a gate insulator layer interposed between the gate electrode and the layer of active semiconductor material.

14. The display defined in claim 12 , further comprising:
a passivation layer interposed between the layer of dielectric material and the gate electrode.

15. The display defined in claim 12 , further comprising:
an additional layer of dielectric material formed on the layer of dielectric material, wherein the third metal layer is interposed between the layer of dielectric material and the additional layer of dielectric material.

16. The display defined in claim 15 , further comprising:
a planarization layer formed on the additional layer of dielectric material, wherein the second metal layer is interposed between the additional layer of dielectric material and the planarization layer.

17. The display defined in claim 16 , further comprising:
a fourth metal layer formed over the planarization layer, wherein the planarization layer is interposed between the fourth metal layer and the second metal layer.

18. The display circuitry defined in claim 1 , wherein the conductive routing structures formed by the first metal layer in the inactive area comprise a first plurality of adjacent routing wires separated by gaps, wherein the conductive routing structures formed by the second metal layer in the inactive area comprise a second plurality of adjacent routing wires, and wherein at least one of the routing wires in the second plurality is aligned with one of the gaps between two of the routing wires in the first plurality.

19. The display circuitry defined in claim 1 , wherein the passivation layer is interposed between the gate insulator layer and the first dielectric layer, the first dielectric layer is interposed between the passivation layer and the second dielectric layer,

Assignees

• Apple Inc

Inventors

• Chen yu cheng
• Chang Shih-Chang
• Osawa Hiroshi
• Chang Ting-Kuo

Classifications

• H01L27/1248

  Electricity · mapped topic

• H01L29/78633

  Electricity · mapped topic

• H01L27/124 Primary

  Electricity · mapped topic

• H01L29/78645

  Electricity · mapped topic

• H10D30/6733

  Multi-gate TFTs · CPC title