Inductive testing probe apparatus for testing semiconductor die and related systems and methods

Patent metadata

Field	Value
Publication number	US-10852344-B2
Application number	US-201715839559-A
Country	US
Kind code	B2
Filing date	Dec 12, 2017
Priority date	Dec 12, 2017
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

A testing probe apparatus for testing die. The testing probe may include a probe interface and a carrier for supporting at least one die comprising 3DI structures. The probe interface may be positionable on a first side of the at least one die and include a voltage source and at least one first inductor operably coupled to the voltage source. A voltage sensor and at least one second inductor coupled to the voltage sensor may be disposed on a second opposing side of the at least one die. The voltage source of the probe interface may be configured to inductively cause a voltage within the 3DI structures of the at least one die via the at least one first inductor. The voltage sensor may be configured to sense a voltage within the at least one 3DI structure via the at least one second inductor. Related systems and methods are also disclosed.

First claim

What is claimed is:

1. A testing probe apparatus for testing at least one die, the testing probe apparatus comprising:
at least one first inductor for positioning on a first side of at least one 3D Interconnect structure of the at least one die;
a voltage source operably coupled to the at least one first inductor;
at least one second inductor for positioning on a second opposite side of the at least one 3D Interconnect structure of the at least one die; and a voltage sensor operably coupled to the at least one second inductor;
wherein the at least one first inductor is configured to generate a magnetic field responsive to the voltage source to cause a voltage within the 3D Interconnect structure and the voltage sensor is configured to detect a voltage within the 3D Interconnect structure via the at least one second inductor.

2. The testing probe apparatus of claim 1 , wherein the at least one first inductor comprises a single first inductor operably coupled to the voltage source, and wherein the at least one second inductor comprises a single second inductor operably coupled to the voltage sensor.

3. The testing probe apparatus of claim 1 , wherein the at least one first inductor comprises a first array of inductors coupled to the voltage source and correlating to a plurality of 3D Interconnect structures of the at least one die, and wherein the at least one second inductor comprises a second array of inductors coupled to the voltage sensor and corresponding to the first array of inductors.

4. The testing probe apparatus of claim 1 , wherein the at least one first inductor is carried by a pick arm.

5. The testing probe apparatus of claim 1 , wherein the at least one first inductor comprises a voltage biased probe card.

6. The testing probe apparatus of claim 1 , further comprising:
a first body of dielectric material at least partially surrounding at least a first distal tip of the at least one first inductor; and
a second body of dielectric material at least substantially surrounding at least a second distal tip of the at least one second inductor.

7. A testing probe system for testing die of a wafer, the testing probe system comprising:
a first probe interface for positioning on a first side of at least one die of the wafer comprising 3D Interconnect structures, the first probe interface comprising: a voltage source; and
at least one first inductor operably coupled to the voltage source; and a carrier for supporting the wafer on an opposing side thereof from the first probe interface; and a second probe interface on an opposing side of the carrier from the first probe interface a voltage sensor; and
at least one second inductor operably coupled to the voltage sensor, wherein the voltage source of the first probe interface is configured to inductively cause a voltage within at least one 3D Interconnect structure of the die via the at least one first inductor, and wherein the voltage sensor of the carrier is configured to detect a voltage within the at least one 3D Interconnect structure via the at least one second inductor.

8. The testing probe system of claim 7 , wherein the first probe interface comprises a probe card having a first array of inductors correlated to a pattern of 3D Interconnect structures of at least one die of the wafer and operably coupled to the voltage source.

9. The testing probe system of claim 7 , wherein the at least one second inductor comprises an array of inductors correlated to a pattern of 3D Interconnect structures of at least one die of the wafer and operably coupled to the voltage sensor, the array of inductors supported by the carrier.

10. The testing probe system of claim 7 , further comprising a first body of dielectric material at least substantially surrounding at least a first distal tip of the at least one first inductor and a second body of dielectric material at least substantially surrounding at least a second distal tip of the at least one second inductor.

11. The testing probe system of claim 7 , wherein the carrier comprises a film frame.

12. The testing probe system of claim 7 , wherein the carrier comprises a cavity carrier comprising cavities for receiving pillars of the 3D Interconnect structures.

13. The testing probe system of claim 7 , wherein the carrier comprises the voltage sensor of the second probe interface.

14. The testing probe system of claim 7 , wherein the first probe interface comprises a voltage biased probe card.

15. The testing probe system of claim 7 , wherein the carrier comprises a wafer chuck.

16. The testing probe system of claim 7 , further comprising a test controller operably coupled to the first probe interface and the second probe interface, wherein the test controller is configured to provide a first output signal to the voltage source of the first probe interface to activate the voltage source and generate a magnetic field around the at least one first inductor, and wherein the test controller is configured to provide a second output signal to the voltage sensor of the second probe interface to activate the voltage sensor.

17. The testing probe system of claim 16 , wherein the test controller is configured to receive an input signal from the voltage sensor of the second probe interface and, responsive to the received input signal, the test controller is configured to determine electrical performance data of the at least one 3D Interconnect structure of the die.

18. The testing probe system of claim 17 , wherein the test controller is further configured to determine, based on the determined electrical performance data of the at least one 3DI structure of the die, whether the die includes one or more defects.

19. A method of testing at least one die, the method comprising: positioning a first probe interface proximate at least one 3D Interconnect structure on a first side of the at least one die without physically contacting the at least one 3D Interconnect structure; positioning a second probe interface proximate the at least one 3D Interconnect structure on a second, opposing side of the at least one die without physically contacting the at least one 3D Interconnect structure;
generating an electromagnetic field within at least a first inductor of the first probe interface proximate the at least one 3D Interconnect structure;
initiating a voltage within the at least one 3D Interconnect structure responsive to the electromagnetic field;
sensing a voltage across the at least one 3D Interconnect structure with at least a second inductor of the second probe interface; and
determining whether the at least one 3D Interconnect structure includes one or more defects based at least in part on the sensed voltage.

20. The method of claim 19 , wherein positioning a first probe interface proximate the at least one 3D Interconnect structure comprises positioning a first probe card carrying a first array of inductors.

21. The method of claim 19 , wherein positioning a first probe interface proximate the at least one 3D Interconnect structure comprises positioning a voltage biased probe card.

22. The method of claim 19 , wherein positioning a second probe interface on a second opposing side of the at least one die comprises positioning a second probe card carrying a second array of inductors.

23. The method of claim 19 , wherein positioning a second probe interface on a second opposing side of the at least one die comprises positioning the second opposing side of the at least one die on a

Assignees

• Micron Technology Inc

Inventors

• Lindenberg Tony M
• Bossart Kurt J
• Hacker Jonathan S
• Tiwari Chandra S

Classifications

• H10P72/0611

  Sorting devices · CPC title

• H10P72/0606

  Position monitoring, e.g. misposition detection or presence detection · CPC title

• H10P72/53

  using optical controlling means · CPC title

• G01R31/2889 Primary

  Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence) · CPC title

• G01R31/2865

  Holding devices, e.g. chucks; Handlers or transport devices (having contacts G01R31/2863) · CPC title