Semiconductor device test apparatuses

Patent metadata

Field	Value
Publication number	US-9733304-B2
Application number	US-201414495025-A
Country	US
Kind code	B2
Filing date	Sep 24, 2014
Priority date	Sep 24, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

Apparatus for testing semiconductor devices comprising die stacks, the apparatus comprising a substrate having an array of pockets in a surface thereof arranged to correspond to conductive elements protruding from a semiconductor device to be tested. The pockets include conductive contacts with traces extending to conductive pads, which may be configured as test pads, jumper pads, edge connects or contact pads. The substrate may comprise a semiconductor wafer or wafer segment and, if the latter, multiple segments may be received in recesses in a fixture. Testing may be effected using a probe card, a bond head carrying conductive pins, or through conductors carried by the fixture.

First claim

What is claimed is:

1. A semiconductor device test apparatus, comprising:
at least one substrate including at least one test site, the at least one substrate comprising one of a semiconductor wafer and a segment of a semiconductor wafer;
the at least one test site including an array of pockets, each pocket of the array sized and configured for at least partially receiving a single conductive element protruding from a semiconductor device to be tested on the at least one test site; and
a conductive contact within each pocket and located at least on the bottom of the pocket coupled to a conductive trace extending to a conductive pad offset from the array of pockets.

2. The apparatus of claim 1 , wherein the at least one substrate comprises a segment of a semiconductor wafer in the form of a strip of semiconductor material having at least one row of test sites thereon.

3. The apparatus of claim 2 , wherein the at least one substrate comprises a number of substrates, and further comprising a fixture configured with a number of recesses, each recess sized and configured to at least partially receive a substrate of the number of substrates, at least some of the recesses having a substrate at least partially received therein.

4. The apparatus of claim 3 , wherein the conductive pads comprise edge connects located proximate at least one side of the strip of semiconductor material comprising a substrate, the edge connects being removably coupled to conductors carried by the fixture.

5. The apparatus of claim 4 , further comprising test equipment selectively couplable to a group of conductors removably coupled to edge connects associated with each test site.

6. The apparatus of claim 1 , wherein the at least one substrate comprises a segment of a semiconductor wafer bearing a single test site.

7. The apparatus of claim 6 , wherein the at least one substrate comprises a number of substrates, and further comprising a fixture configured with a number of recesses, each recess sized and configured to at least partially receive a substrate of the number of substrates, at least some of the recesses having a substrate at least partially received therein.

8. The apparatus of claim 7 , wherein the conductive pads comprise jumper pads, and further comprising conductive test pads adjacent each recess, the jumper pads being electrically connected to the conductive test pads with wire bonds.

9. The apparatus of claim 7 , wherein the conductive pads are located on a surface of each substrate opposite a surface in which the pockets are located, the conductive traces comprise conductive vias extending from the conductive contacts to the conductive pads, and the fixture further comprises contact pads located on bottom surfaces of the recesses in a configuration aligned with the conductive pads, the contact pads having conductive traces extending to test pads on one of a surface of the fixture having recesses therein, an opposing surface of the fixture, and a side surface of the fixture.

10. The apparatus of claim 1 , wherein the conductive pads are located on a surface of the substrate in which the pockets are located, the conductive pads laterally offset from a footprint of a semiconductor device having conductive elements to be at least partially received in the pockets.

11. The apparatus of claim 10 , further comprising a probe card for simultaneously contacting conductive pads associated with at least one test site, the probe card configured, for testing a semiconductor device located on the at least one test site, with a compliant material for contacting a top of the semiconductor device and a number of contact pins laterally offset from the compliant material and arranged for contact with the conductive pads when the compliant material is aligned with the semiconductor device.

12. The apparatus of claim 11 , wherein the probe card is configured for simultaneously contacting multiple semiconductor devices for testing.

13. The apparatus of claim 12 , further comprising test equipment operably couplable to the probe card through a multiplexor for selective testing of each of the multiple semiconductor devices.

14. The apparatus of claim 10 , further comprising a device comprising
a bond head and a pick and place head, the bond head having a first set of contact pins arranged for contact with the conductive pads when conductive elements of a semiconductor device aligned with the bond head are received in the array of pockets and a second set of contact pins laterally offset from the first set and operably coupled thereto, contact pins of the second set arranged for contact with test pads on a surface of a holder on which the substrate is placed.

15. The apparatus of claim 2 , further comprising a carrier having the substrate disposed therein and a clamp head extending over and removably coupled to the carrier, the clamp head having compliant material on a surface thereof facing the substrate at least over test site locations.

16. A semiconductor device test apparatus, comprising:
at least one substrate comprising at least one test site including an array of pockets, each pocket of the array sized and configured for at least partially receiving a single conductive element protruding from a semiconductor device to be tested on the at least one test site; and
a conductive contact within each pocket and located at least on the bottom of the pocket coupled to a conductive trace extending to a conductive pad offset from the array of pockets, wherein the conductive pads are located on a surface of the substrate in which the pockets are located, the conductive pads laterally offset from a footprint of a semiconductor device having conductive elements to be at least partially received in the pockets; and
a probe card for simultaneously contacting conductive pads associated with at least one test site, the probe card configured, for testing a semiconductor device located on the at least one test site, with a compliant material for contacting a top of the semiconductor device and a number of contact pins laterally offset from the compliant material and arranged for contact with the conductive pads when the compliant material is aligned with the semiconductor device.

17. The apparatus of claim 16 , wherein the probe card is configured for simultaneously contacting multiple semiconductor devices for testing.

18. The apparatus of claim 17 , further comprising test equipment operably couplable to the probe card through a multiplexor for selective testing of each of the multiple semiconductor devices.

19. A semiconductor device test apparatus, comprising:
at least one substrate comprising at least one test site including an array of pockets, each pocket of the array sized and configured for at least partially receiving a single conductive element protruding from a semiconductor device to be tested on the at least one test site; and
a conductive contact within each pocket and located at least on the bottom of the pocket coupled to a conductive trace extending to a conductive pad offset from the array of pockets, wherein the conductive pads are located on a surface of the substrate in which the pockets are located, the conductive pads laterally offset from a footprint of a semiconductor device having conductive elements to be at least partially received in the pockets; and
a device comprising a bond head and a pick and place head, the bond head having a first set of contact pins arranged for contact with the conductive pads when conductive elements of a semiconductor device aligned with

Assignees

• Micron Technology Inc

Inventors

• Gandhi Jaspreet S
• Koopmans Michel
• Derderian James M

Classifications

• G01R31/2887 Primary

  involving moving the probe head or the IC under test; docking stations (moving single probes G01R1/06705; moving individual probes in multiple probes G01R1/07392) · CPC title

• G01R1/07307

  with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card · CPC title

• G01R31/2884

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title