Three-dimensional memory devices having through stair contacts and methods for forming the same

Patent metadata

Field	Value
Publication number	US-10847539-B2
Application number	US-201916292268-A
Country	US
Kind code	B2
Filing date	Mar 4, 2019
Priority date	Jan 2, 2019
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

Embodiments of three-dimensional (3D) memory devices having through stair contacts (TSCs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of interleaved dielectric layers and sacrificial layers is formed on a substrate. A staircase structure is formed on one side of the dielectric stack. A dummy hole extending vertically through the staircase structure and reaching the substrate is formed. A spacer having a hollow core is formed in the dummy hole. A TSC in contact with the substrate is formed by depositing a conductor layer in the hollow core of the spacer. The TSC extends vertically through the staircase structure.

First claim

What is claimed is:

1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a dielectric stack on a substrate, the dielectric stack comprising a plurality of interleaved dielectric layers and sacrificial layers;
forming a staircase structure on at least one side of the dielectric stack, the staircase structure comprising a plurality of landing areas at levels below a top surface of dielectric stack;
forming a dummy hole extending vertically through at least one of the plurality of landing areas of the staircase structure and reaching the substrate;
forming a spacer in the dummy hole, the spacer having a hollow core; and
forming a through stair contact (TSC) in direct contact with the substrate by depositing a conductor layer in the hollow core of the spacer, the TSC extending vertically through the staircase structure.

2. The method of claim 1 , further comprising prior to forming the TSC, forming a plurality of word lines by replacing the sacrificial layers in the dielectric stack with conductor layers.

3. The method of claim 2 , further comprising forming a plurality of word line contacts each in contact with a respective one of the word lines simultaneously with forming the TSC.

4. The method of claim 1 , further comprising after forming the TSC, forming a plurality of word lines by replacing the sacrificial layers in the dielectric stack with conductor layers.

5. The method of claim 1 , wherein forming the spacer comprising depositing a dielectric layer in the dummy hole.

6. The method of claim 1 , further comprising forming a second dummy hole outside the dielectric stack simultaneously with forming the dummy hole.

7. The method of claim 6 , further comprising forming a peripheral contact by depositing a second conductor layer in the second dummy hole simultaneously with forming the TSC, wherein the peripheral contact is in contact with the substrate.

8. The method of claim 7 , wherein the first and second conductor layers comprise a same material.

9. A method for forming a three-dimensional (3D) memory device, comprising:
forming a dielectric stack comprising a plurality of interleaved dielectric layers and sacrificial layers on a substrate;
forming a staircase structure on at least one side of the dielectric stack, the staircase structure comprising a plurality of landing areas at levels below a top surface of dielectric stack;
forming a dummy channel structure reaching the substrate, the dummy channel structure extending vertically through at least one of the plurality of landing areas of the staircase structure;
forming a spacer by removing part of the dummy channel structure, the spacer having a hollow core; and
forming a through stair contact (TSC) in direct contact with the substrate by depositing a conductor layer in the hollow core of the spacer, the TSC extending vertically through the staircase structure.

10. The method of claim 9 , further comprising prior to forming the spacer, forming a plurality of word lines by replacing the sacrificial layers in the dielectric stack with conductor layers.

11. The method of claim 10 , further comprising forming a plurality of word line contacts each in contact with a respective one of the word lines simultaneously with forming the TSC.

12. The method of claim 9 , further comprising after forming the TSC, forming a plurality of word lines by replacing the sacrificial layers in the dielectric stack with conductor layers.

13. The method of claim 9 , wherein forming the spacer comprises etching an opening through the dummy channel structure to reach the substrate.

14. The method of claim 9 , further comprising forming a second spacer outside the dielectric stack simultaneously with forming the spacer.

15. The method of claim 14 , further comprising forming a peripheral contact by depositing a second conductor layer in the second spacer simultaneously with forming the TSC, wherein the peripheral contact is in contact with the substrate.

16. The method of claim 15 , wherein the first and second conductor layers comprise a same material.

17. A three-dimensional (3D) memory device, comprising:
a substrate;
a memory stack on the substrate comprising a plurality of interleaved conductor layers and dielectric layers;
a staircase structure on one side of the memory stack, the staircase structure comprising a plurality of landing areas at levels below a top surface of dielectric stack; and
a through stair contact (TSC) extending vertically through at least one of the plurality of landing areas of the staircase structure of the memory stack, wherein the TSC is in direct contact with the substrate.

18. The 3D memory device of claim 17 , further comprising:
a peripheral contact outside of the memory stack, wherein the peripheral contact is in contact with the substrate.

19. The 3D memory device of claim 18 , wherein the peripheral contact and the TSC comprise a same material.

20. The 3D memory device of claim 18 , wherein a sidewall of each of the TSC and peripheral contact is surrounded by a spacer with a nominally same thickness.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wei Qinxiang
• Sun Jianhua
• Xia Ji

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title