Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling same

Patent metadata

Field	Value
Publication number	US-10847467-B2
Application number	US-201916658866-A
Country	US
Kind code	B2
Filing date	Oct 21, 2019
Priority date	Mar 27, 2018
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

An embedded multi-die interconnect bridge (EMIB) die is configured with power delivery to the center of the EMIB die and the power is distributed to two dice that are interconnected across the EMIB die.

First claim

The invention claimed is:

1. A bridge die, comprising:
a first outer portion, a second outer portion, and a central portion from a plan view perspective, the central portion between the first outer portion and the second outer portion;
a plurality of power-delivery micro-vias in the central portion;
a first plurality of power-distribution micro-vias in the first outer portion, the first plurality of power-distribution micro-vias electrically coupled to the plurality of power-distribution micro-vias; and
a second plurality of power-distribution micro-vias in the second outer portion, the second plurality of power-distribution micro-vias electrically coupled to the plurality of power-delivery micro-vias, and the second plurality of power-distribution micro-vias having a total number of power-distribution micro-vias less than a total number of power-distribution micro-vias of the first plurality of power-distribution micro-vias.

2. The bridge die of claim 1 , wherein the first and second pluralities of power-distribution micro-vias are electrically are coupled to the plurality of power-delivery micro-vias by one or more power rails.

3. The bridge die of claim 2 , wherein the one or more power rails are beneath the first and second pluralities of power-distribution micro-vias and the plurality of power-delivery micro-vias.

4. The bridge die of claim 1 , wherein the central portion comprises one or more power bumps.

5. The bridge die of claim 4 , wherein the one or more power bumps are electrically connected to the plurality of power-delivery micro-vias by a power header.

6. The bridge die of claim 4 , wherein the one or more power bumps are on a periphery of the central portion.

7. The bridge die of claim 1 , wherein the first outer portion and the second outer portion further comprise ground micro-vias.

8. An embedded multi-die interconnect bridge package, comprising:
a packaging material comprising a plurality of build-up layers;
a bridge die embedded in the packaging material, the bridge die comprising:
a first outer portion, a second outer portion, and a central portion from a plan view perspective, the central portion between the first outer portion and the second outer portion;
a plurality of power-delivery micro-vias in the central portion;
a first plurality of power-distribution micro-vias in the first outer portion, the first plurality of power-distribution micro-vias electrically coupled to the plurality of power-distribution micro-vias; and
a second plurality of power-distribution micro-vias in the second outer portion, the second plurality of power-distribution micro-vias electrically coupled to the plurality of power-delivery micro-vias, and the second plurality of power-distribution micro-vias having a total number of power-distribution micro-vias less than a total number of power-distribution micro-vias of the first plurality of power-distribution micro-vias; and

a first semiconductive device on the packaging material, the first semiconductive device electrically coupled to the first outer portion of the bridge die; and
a second semiconductive device on the packaging material, the second semiconductive device electrically coupled to the second outer portion of the bridge die.

9. The embedded multi-die interconnect bridge package of claim 8 , wherein the first semiconductive device is a mother die, and the second semiconductive device is a daughter die.

10. The embedded multi-die interconnect bridge package of claim 8 , wherein the first semiconductive device is a logic die, and the second semiconductive device is a memory die.

11. The embedded multi-die interconnect bridge package of claim 8 , wherein the packaging material comprises a top dielectric layer.

12. The embedded multi-die interconnect bridge package of claim 8 , further comprising:
a dielectric build-up layer is between the bridge die and the first semiconductive device, and between the bridge die and the second semiconductive device.

13. The embedded multi-die interconnect bridge package of claim 8 , wherein the packaging material comprises a power delivery via.

14. The embedded multi-die interconnect bridge package of claim 13 , wherein the first semiconductive device is electrically coupled to the power delivery via of the packaging material.

15. The embedded multi-die interconnect bridge package of claim 8 , wherein the first and second pluralities of power-distribution micro-vias of the bridge die are electrically are coupled to the plurality of power-delivery micro-vias of the bridge die by one or more power rails in the bridge die.

16. The embedded multi-die interconnect bridge package of claim 15 , wherein the one or more power rails of the bridge die are beneath the first and second pluralities of power-distribution micro-vias and the plurality of power-delivery micro-vias of the bridge die.

17. The embedded multi-die interconnect bridge package of claim 8 , wherein the central portion of the bridge die comprises one or more power bumps.

18. The embedded multi-die interconnect bridge package of claim 17 , wherein the one or more power bumps of the bridge die are electrically connected to the plurality of power-delivery micro-vias of the bridge die by a power header.

19. The embedded multi-die interconnect bridge package of claim 17 , wherein the one or more power bumps of the bridge die are on a periphery of the central portion of the bridge die.

20. The embedded multi-die interconnect bridge package of claim 8 , wherein the first outer portion and the second outer portion of the bridge die further comprise ground micro-vias.

Assignees

• Intel Corp

Inventors

• Collins Andrew
• Mallik Debendra
• Manusharow Mathew J
• Xie Jianyong

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title