Apparatuses and methods for single level cell caching

Patent metadata

Field	Value
Publication number	US-10846008-B2
Application number	US-201916455605-A
Country	US
Kind code	B2
Filing date	Jun 27, 2019
Priority date	Oct 27, 2016
Publication date	Nov 24, 2020
Grant date	Nov 24, 2020

Abstract

Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.

First claim

What is claimed is:

1. A method comprising:
receiving, at a memory device, a first set of data to be stored in a first page of multilevel memory cells;
storing a copy of the first set of data in a page of single level memory cells;
subsequently storing the first set of data in the first page of the multilevel memory cells;
receiving, at the memory device, a second set of data to be stored in a second page of the multilevel memory cells; and
storing the second set of data directly in the second page of the multilevel memory cells without storing a copy of the second set of data before storing the second set of data in the second page of the multilevel memory cells.

2. The method of claim 1 , further comprising:
determining whether the first set of data stored in the first page of multilevel memory cells is lost; and
responsive to determining that the first set of data stored in the first page of multilevel memory cells is lost, copying the first set of data from the page of single level memory cells to the first page of the multilevel memory cells.

3. The method of claim 2 , wherein determining whether the first set of data stored in the first page of multilevel memory cells is lost comprises determining whether a power loss event occurred while storing the second set of data in the second page of the multilevel memory cells.

4. The method of claim 1 , further comprising:
erasing the first set of data from the page of single level memory cells.

5. The method of claim 1 , wherein the multilevel memory cells are each configured to store at least two bits.

6. The method of claim 1 , further comprising:
responsive to storing the first set of data in the page of single level memory cells, providing a confirmation message.

7. An apparatus comprising:
a memory array comprising a page of a block of single level memory cells and a block of multilevel memory cells, wherein the block of multilevel memory cells includes a lower page and an upper page,
wherein the page of the block of single level memory cells stores a copy of a first set of data, wherein the lower page of the block of multilevel memory cells subsequently receives the first set of data, and
the upper page of the block of multilevel memory cells is configured to store a second set of data, wherein the apparatus does not store a copy of the second set of data when the second set of data is being written in the upper page of the block of multilevel memory cells.

8. The apparatus of claim 7 , further comprising a control circuit configured to update one or more page tables responsive to storing the first set of data or the second set of data.

9. The apparatus of claim 8 , wherein the control circuit is further configured to erase the page of the Hock of single level memory cells responsive to storing the second set of data in the upper page of the block of multilevel memory cells.

10. The apparatus of claim 8 , wherein the control circuit is further configured to provide a confirmation message responsive to storing the first set of data in the page of the single level memory cells.

11. The apparatus of claim 8 , wherein the control circuit is further configured to:
detect a power loss event while storing the second set of data in the upper page of the block of multilevel memory cells; and
copy the first set of data from the page of the block of single level memory cells to the lower page of the block multilevel memory cells responsive to detecting the power loss event.

12. The apparatus of claim 7 , wherein the block of multilevel memory cells comprises memory cells configured to store at least three bits.

13. An apparatus comprising:
a memory array comprising a page of a block of single level memory cells and a block of multilevel memory cells, wherein the block of multilevel memory cells includes a lower page and an upper page; and
a control circuit configured to:
update one or more page tables responsive to storing at least a first set of data into the page of the block of single level memory cells,
store a second set of data directly in the upper page of the block of multilevel memory cells without storing a copy of the second set of data in the page of the block of single level memory cells, and
erase the page of the block of single level memory cells responsive to storing the second set of data in the upper page of the block of multilevel memory cells.

14. The apparatus of claim 13 , wherein the control circuit is configured to store the first set of data into the page of the block of single level memory cells, wherein the lower page of the block of multilevel memory cells subsequently receives the first set of data.

15. The apparatus of claim 13 , wherein the Hock of multilevel memory cells comprises memory cells configured to store at least three bits.

16. The apparatus of claim 13 , wherein the control circuit is further configured to provide a confirmation message responsive to storing the first set of data in the page of the block of single level memory cells.

17. The apparatus of claim 13 , wherein the control circuit is further configured to detect a power loss event while storing the second set of data in the upper page of the Hock of multilevel memory cells.

18. The apparatus of claim 17 , wherein the control circuit is configured to copy the first set of data from the page of the block of single level memory cells to the lower page of the block of multilevel memory cells responsive to detecting the power loss event.

19. The apparatus of claim 13 , wherein the control circuit is configured to continue storing the second set of data in the upper page of the block of multilevel memory cells responsive to the first set of data being copied from the page of the block of single level memory cells to the lower page of the block of multilevel memory cells.

20. The apparatus of claim 19 , wherein the control circuit is configured to erase the page of the block of single level memory cells responsive to completion of storing the second set of data in the upper page of the block of multilevel memory cells.

Assignees

• Micron Technology Inc

Inventors

• Doyle Daniel

Classifications

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G06F3/0644 Primary

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G11C2211/5641

  Multilevel memory having cells with different number of storage levels · CPC title