Apparatuses and methods for single level cell caching

Patent metadata

Field	Value
Publication number	US-10048887-B2
Application number	US-201615336071-A
Country	US
Kind code	B2
Filing date	Oct 27, 2016
Priority date	Oct 27, 2016
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.

First claim

What is claimed is:

1. An apparatus comprising:
a memory array comprising a block of single level memory cells and a block of multilevel memory cells; and
a control circuit configured to receive a first set of data to be written into the memory array, store a copy of the first set of data in a page of the block of single level memory cells, and subsequently store the first set of data in a lower page of the block of multilevel memory cells, the control circuit further configured to receive a second set of data and store the second set of data directly in an upper page of the multilevel memory cells without storing a copy of the second set of data in the page of the block of single level memory cells.

2. The apparatus of claim 1 , wherein the control circuit is further configured to update one or more page tables responsive to storing the first set of data or the second set of data.

3. The apparatus of claim 1 , wherein the block of multilevel memory cells comprises memory cells configured to store at least three bits.

4. The apparatus of claim 1 , wherein the control circuit is further configured to erase the page of the block of single level memory cells responsive to storing the second set of data in the upper page of the block of multilevel memory cells.

5. The apparatus of claim 1 , wherein the control circuit is further configured to provide a confirmation message responsive to storing the first set of data in the page of the single level memory cells.

6. The apparatus of claim 1 , wherein the control circuit is further configured to:
detect a power loss event while storing the second set of data in the upper page of the block of multilevel memory cells; and
copy the first set of data from the page of the block of single level memory cells to the lower page of the block multilevel memory cells responsive to detecting the power loss event.

Assignees

• Micron Technology Inc

Inventors

• Doyle Daniel

Classifications

• G11C11/56

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G06F3/064

  Management of blocks · CPC title