Apparatuses and methods for single level cell caching

Patent metadata

Field	Value
Publication number	US-10353615-B2
Application number	US-201816102030-A
Country	US
Kind code	B2
Filing date	Aug 13, 2018
Priority date	Oct 27, 2016
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.

First claim

What is claimed is:

1. An apparatus comprising:
a control circuit configured to receive a first set of data and store a copy of the first set of data in a page of a block of single level memory cells, and subsequently store the first set of data in a lower page of a block of multilevel memory cells,
wherein the control circuit is configured to:
update one or more page tables responsive to storing at least the first set of data,
receive a second set of data and store the second set of data directly in an upper page of the multilevel memory cells without storing a copy of the second set of data in the page of the block of single level memory cells, and
erase the page of the block of single level memory cells responsive to storing the second set of data in the upper page of the block of multilevel memory cells.

2. The apparatus of claim 1 , wherein the block of multilevel memory cells comprises memory cells configured to store at least three bits.

3. The apparatus of claim 1 , wherein the control circuit is further configured to provide a confirmation message responsive to storing the first set of data in the page of the single level memory cells.

4. The apparatus of claim 1 , wherein the control circuit is further configured to:
detect a power loss event while storing the second set of data in the upper page of the block of multilevel memory cells; and
copy the first set of data from the page of the block of single level memory cells to the lower page of the block multilevel memory cells responsive to detecting the power loss event.

5. The apparatus of claim 4 , wherein the control circuit is configured to continue storing the second set of data in the upper page of the multilevel memory cells responsive to the first set of data being copied from the page of the block of single level memory cells to the lower page of the block multilevel memory cells.

6. The apparatus of claim 5 , wherein the control circuit is configured to erase the page of the block of single level memory cells responsive to completion of storing the second set of data in the upper page of the multilevel memory cells.

7. A method comprising:
storing a copy of a first set of data in a page of a block of single level memory cells;
subsequently to storing the copy of the first set of data in the page of the block of single level memory cells, receiving the first set of data at a lower page of a block of multilevel memory cells;
storing a second set of data in an upper page of the block of multilevel memory cells, wherein the page of the block of single level memory cells does not store a copy of the second set of data;
updating one or more page tables responsive to storing the first set of data or the second set of data; and
erasing the page of the block of single level memory cells responsive to storing the second set of data in the upper page of the block of multilevel memory cells.

8. The method of claim 7 , further comprising providing a confirmation message responsive to storing the first set of data in the page of the single level memory cells.

9. The method of claim 7 , further comprising:
detecting a power loss event while storing the second set of data in the upper page of the block of multilevel memory cells; and
copying the first set of data from the page of the block of single level memory cells to the lower page of the block multilevel memory cells responsive to detecting the power loss event.

10. The method of claim 9 , further comprising continuing to store the second set of data in the upper page of the multilevel memory cells responsive to the first set of data being copied from the page of the block of single level memory cells to the lower page of the block multilevel memory cells.

11. An apparatus comprising:
a control circuit configured to receive a first set of data and store a copy of the first set of data in a page of a block of single level memory cells, and subsequently store the first set of data in a lower page of a block of multilevel memory cells,
wherein the control circuit is configured to:
update one or more page tables responsive to storing at least the first set of data,
receive a second set of data and store the second set of data directly in an upper page of the multilevel memory cells without storing a copy of the second set of data in the page of the block of single level memory cells,
detect a power loss event while storing the second set of data in the upper page of the block of multilevel memory cells, and
copy the first set of data from the page of the block of single level memory cells to the lower page of the block multilevel memory cells responsive to detecting the power loss event.

12. A method comprising:
storing a copy of a first set of data in a page of a block of single level memory cells;
subsequently to storing the copy of the first set of data in the page of the block of single level memory cells, receiving the first set of data at a lower page of a block of multilevel memory cells;
storing a second set of data in an upper page of the block of multilevel memory cells, wherein the page of the block of single level memory cells does not store a copy of the second set of data;
updating one or more page tables responsive to storing the first set of data or the second set of data;
detecting a power loss event while storing the second set of data in the upper page of the block of multilevel memory cells; and
copying the first set of data from the page of the block of single level memory cells to the lower page of the block multilevel memory cells responsive to detecting the power loss event.

Assignees

• Micron Technology Inc

Inventors

• Doyle Daniel

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title

• G11C11/5678

  using amorphous/crystalline phase transition storage elements · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title