IGBT with dV/dt controllability

Patent metadata

Field	Value
Publication number	US-10840362-B2
Application number	US-201816168136-A
Country	US
Kind code	B2
Filing date	Oct 23, 2018
Priority date	Oct 24, 2017
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

A power semiconductor device includes an active cell region with a drift region, and IGBT cells at least partially arranged within the active cell region. Each IGBT cell includes at least one trench extending into the drift region along a vertical direction, an edge termination region surrounding the active cell region, and a transition region arranged between the active cell region and the edge termination region. The transition region has a width along a lateral direction from the active cell region towards the edge termination region. At least some of the IGBT cells are arranged within, or, respectively, extend into the transition region. An electrically floating barrier region of each IGBT cell is arranged within the active cell region and in contact with at least some of the trenches of the IGBT cells. The electrically floating barrier region does not extend into the transition region.

First claim

What is claimed is:

1. A power semiconductor device, comprising a first load terminal and a second load terminal, the power semiconductor device being configured to conduct a load current along a vertical direction between the first and second load terminals and comprising:
an active cell region with a drift region of a first conductivity type;
an edge termination region having a well region of a second conductivity type;
a plurality of IGBT cells arranged within the active cell region, wherein each of the IGBT cells comprises a plurality of trenches extending into the drift region along the vertical direction and laterally confining a plurality of mesas;
the plurality of trenches comprising:
at least one control trench having a control electrode;
at least one dummy trench having a dummy electrode electrically coupled to the control electrode;
at least one source trench having a source electrode electrically connected with the first load terminal;
the plurality of mesas comprising:
at least one active mesa arranged between the at least one control trench and the at least one source trench;
at least one inactive mesa arranged adjacent to the at least one dummy trench;
an electrically floating barrier region of the second conductivity type, wherein at least both a bottom of the dummy trench and a bottom of the source trench extend at least partially into the electrically floating barrier region, and wherein a portion of the drift region located in a lateral direction between the electrically floating barrier region and the well region has a lateral extension of at least 1 μm in the lateral direction.

2. The power semiconductor device of claim 1 , wherein the electrically floating barrier region is spatially confined, in and against the vertical direction, by the drift region.

3. The power semiconductor device of claim 1 , wherein the barrier region is formed as a laterally structured layer that extends throughout the entire active cell region.

4. The power semiconductor device of claim 1 , wherein the IGBT cells are configured with a lateral structure of the barrier region according to a first layout having a first pitch, and wherein the lateral structure of the barrier region is configured according to a second layout, the second layout having a second pitch at least twice as large as the first pitch.

5. The power semiconductor device of claim 4 , wherein the lateral structure of the barrier region is formed by a plurality of pass-through passages.

6. The power semiconductor device of claim 5 , wherein each of the plurality of the pass-through passages is filled by either a section of the drift region or by a section of a trench of a respective one of the IGBT cells.

7. The power semiconductor device of claim 5 , wherein a distance between two arbitrary ones of the pass-through passages that are arranged adjacent to each other is smaller than 1 mm.

8. The power semiconductor device of claim 5 , wherein the barrier region is arranged within a semiconductor layer of the semiconductor body, the semiconductor layer extending entirely and exclusively within the active cell region and having a total volume, wherein the pass-through passages form at least 1% and at most 50% of the total volume, and wherein a remaining volume of the semiconductor layer is formed by semiconductor regions of the second conductivity type.

9. The power semiconductor device of claim 8 , wherein the remaining volume has a dopant concentration greater than 1e14 cm −3 and smaller than 1e17 cm −3 , the dopant concentration being present within an extension along the vertical direction of at least 0.1 μm.

10. The power semiconductor device of claim 5 , wherein the pass-through passages laterally overlap with one or more of the active mesas of the IGBT cells.

11. The power semiconductor device of claim 10 , wherein the pass-through passages laterally overlap, with respect to the total number of active mesas present within the active cell region, with at least 1% and at most 50% of the active mesas.

12. The power semiconductor device of claim 1 , wherein the barrier region has a resistivity of more than 10 Ωcm and of less than 1000 Ωcm, and/or wherein the barrier region includes boron, aluminum, difluoroboryl, boron trifluoride, or a combination thereof.

13. The power semiconductor device of claim 1 , wherein the barrier region is confined, along the vertical direction, by an upper section of the drift region on a first side and by a lower section of the drift region on a second side, and wherein the upper section forms a transition to channel regions of the IGBT cells.

14. The power semiconductor device of claim 13 , wherein the dopant concentration within the upper section is at least twice as large as within the lower section.

15. The power semiconductor device of claim 1 , wherein the dopant concentration within an upper section of the at least one active mesa is at least twice as large as within a lower section of the at least one active mesa.

16. The power semiconductor device of claim 1 , wherein the dopant concentration within an upper section of the at least one active mesa is at least twice as large as within an upper section of the at least one inactive mesa.

Assignees

• Infineon Technologies Ag

Inventors

• Philippou Alexander
• Bina Markus
• Dainese Matteo
• Jaeger Christian
• Laven Johannes Georg
• Santos Rodriguez Francisco Javier
• Vellei Antonio
• Leendertz Caspar
• Sandow Christian Philipp

Classifications

• H10D30/68

  Floating-gate IGFETs · CPC title

• H10D12/01

  Manufacture or treatment · CPC title

• H10D84/0156

  Manufacturing their doped wells · CPC title

• H10D12/411 Primary

  Insulated-gate bipolar transistors [IGBT] · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title