Power semiconductor device

Patent metadata

Field	Value
Publication number	US-2016336393-A1
Application number	US-201514939119-A
Country	US
Kind code	A1
Filing date	Nov 12, 2015
Priority date	May 12, 2015
Publication date	Nov 17, 2016
Grant date	—

Abstract

The present examples relate to a power semiconductor device. The present examples also relate to a power semiconductor device that maintains a breakdown voltage and reduces a gate capacitance through improving the structure of an Injection Enhanced Gate Transistor (IEGT), and thereby reduces strength of an electric field compared to alternative technologies. Accordingly, the present examples provide a power semiconductor device with a small energy consumption and with an improved switching functionality.

First claim

What is claimed is:

1 . A power semiconductor device comprising:
a substrate having a first surface and a second surface opposite to the first surface; a drift region located on the substrate having a first conductivity type; an emitter electrode located on the first surface of the substrate; a drain electrode located on the second surface of the substrate; an emitter contact region in contact with the emitter electrode; a trench gate structure that surrounds four sides of the emitter contact region; a base region located under the emitter contact region having a second conductivity type; and a floating region located on an exterior region of the trench gate structure that surrounds the trench gate structure and is deeper than the trench gate structure, wherein the floating region is electrically floating and surrounds a bottom surface of the trench gate structure and is separate from the base region, and wherein an impurity concentration of the floating region is lower than an impurity concentration of the base region.

2 . The power semiconductor device of claim 1 , wherein
the trench gate structure comprises a pair of trench gates extending from the substrate surface to the drift region, the emitter contact region comprises a first conductivity type source region and a second conductivity type contact region, the power semiconductor device further comprises a first well region with a first conductivity type configured between the base region and drift region that has a higher impurity concentration than the drift region, and the floating region and the base region are separated by the first well region.

3 . The power semiconductor device of claim 2 , further comprising:
a second conductivity type deep-well region having a greater depth than the floating region; and a pair of dummy trench gates configured not to contact the source region and having a smaller depth than the deep-well region, wherein the floating region and the deep-well region are separated by the pair of dummy trench gates.

4 . The power semiconductor device of claim 1 , further comprising:
a termination region located in the substrate and surrounding a cell region, wherein the cell region comprises the trench gate structure and the floating region, and the termination region comprises a termination ring region and a gate bus line.

5 . The power semiconductor device of claim 1 , further comprising:
a termination ring region located in the substrate; a dummy trench gate located between the floating region and the termination ring region; and a second conductivity type deep-well region located between the dummy trench gate and the termination ring region and having a deeper depth than the dummy trench gate, wherein the deep-well region is electrically connected to the emitter electrode.

6 . The power semiconductor device of claim 5 , further comprising:
a second conductivity type edge base region located between the dummy trench gate and the deep-well region, with a smaller depth than the dummy trench gate.

7 . A power semiconductor substrate comprising:
a substrate comprising a first conductivity type drift region; an emitter electrode located on an upper region of the substrate; a drain electrode located on a lower region of the substrate; a trench emitter structure that is electrically connected to the emitter electrode; a second conductivity type floating region located in the trench emitter structure with a greater depth than the depth of the trench emitter structure; a trench gate structure arranged in an exterior region of the trench emitter structure and surrounding the trench emitter structure; an emitter contact region formed between the trench gate structure and the trench emitter structure and in contact with the emitter electrode; and a second conductivity type base region formed below the emitter contact region, wherein the floating region is electrically floating, and wherein the trench gate structure has a network structure having a net shape whose portions connect with each other, with a planar structure.

8 . The power semiconductor substrate of claim 7 , wherein the floating region is in contact with the drift region and surrounds a bottom corner of the trench emitter structure.

9 . The power semiconductor substrate of claim 7 , wherein the width of the floating region is greater than the width of the base region.

10 . The power semiconductor substrate of claim 7 , wherein
the trench gate structure comprises trench regions, the trench regions comprise a pair of trench gates configured to extend from the substrate surface to the drift region, and the emitter contact region comprises a first conductivity type source region and a second conductivity type contact region.

11 . The power semiconductor substrate of claim 10 , wherein the trench emitter structure is formed between the pair of trench gates and the trench emitter structure is configured not to contact with the source region.

12 . The power semiconductor substrate of claim 7 , further comprising:
a second conductivity type termination ring region formed in the inner substrate; and a dummy trench gate with a deeper depth than the base region, wherein the dummy trench gate is formed between the base region and the termination ring region and is configured not to contact with the source region.

13 . The power semiconductor substrate of claim 7 , wherein
the substrate is divided into a first region and a second region and the first region and the second region are formed alternately on the substrate, the first region comprising the floating region surrounding the trench emitter structure, and the second region comprising the emitter contact region surrounding the trench gate structure.

14 . The power semiconductor substrate of claim 12 , wherein the termination ring region is overextended on the lower side of the dummy trench gate.

15 . A power semiconductor device comprising:
a drift region located on a substrate having a first conductivity type; an emitter electrode located on a first surface of the substrate, comprising an emitter contact region in contact with the emitter electrode; a drain electrode located on a second surface of the substrate, wherein the second surface is opposite to the first surface; a trench gate structure that surrounds the emitter contact region; a base region located under the emitter contact region, having a second conductivity type; and an floating region located on an exterior region, surrounding a bottom surface of, separate from, and deeper than the trench gate structure, wherein the floating region is electrically floating, wherein an impurity concentration of the floating region is lower than an impurity concentration of the base region.

16 . The power semiconductor device of claim 15 , wherein
the trench gate structure comprises a pair of trench gates extending from the substrate surface to the drift region, the emitter contact region comprises a first conductivity type source region and a second conductivity type contact region, the power semiconductor device further comprises a first well region with a first conductivity type configured between the base region and drift region that has a higher impurity concentration than the drift region, and the floating region and the base region are separated by the first well region.

17 . The power semiconductor device of claim 16 , further comprising:
a second conductivity type deep-well region having a greater depth than the floating region; an

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Kim In Su
• Park Jeong Hwan
• Park Seung Sik
• Yang Ha Yong

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title