Formation of copper layer structure with self anneal strain improvement

US10840184B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10840184-B2
Application numberUS-201815870810-A
CountryUS
Kind codeB2
Filing dateJan 12, 2018
Priority dateJun 18, 2015
Publication dateNov 17, 2020
Grant dateNov 17, 2020

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

In a method for manufacturing an interconnect structure, a dielectric layer is removed to form a first recess and a second recess. The first recess is below the second recess. A first metal layer is deposited to fill the first recess and a first portion of the second recess. A carbon-containing layer is deposited over the first metal layer to fill a second portion of the second recess, which is over the first portion. A second metal layer is deposited over the carbon-containing layer to fill a third portion of the second recess, which is over the second portion. A carbon concentration of the carbon-containing layer is greater than a carbon concentration of the first metal layer and a carbon concentration of the second metal layer, and the carbon concentration of the first metal layer is substantially the same as the carbon concentration of the second metal layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for manufacturing an interconnect structure, comprising: removing a portion of a dielectric layer to form a first recess and a second recess in the dielectric layer, wherein the first recess is below the second recess; electroplating a first copper layer to fill the first recess and a first portion of the second recess, such that the first copper layer is in contact with a lower portion of a sidewall of the dielectric layer, and a top surface of the dielectric layer and an upper portion of a sidewall of the dielectric layer are free from coverage of the first copper layer; electroplating a carbon-containing copper layer over the first copper layer in a first plating tank to fill a second portion of the second recess, the second portion of the second recess being over the first portion of the second recess; and electroplating a second copper layer over the carbon-containing copper layer in a second plating tank that is different from the first plating tank to fill a third portion of the second recess, the third portion of the second recess being over the second portion of the second recess, wherein a carbon concentration of the carbon-containing copper layer is greater than a carbon concentration of the first copper layer and a carbon concentration of the second copper layer, and the carbon concentration of the first copper layer is the same as the carbon concentration of the second copper layer. 2. The method of claim 1 , wherein electroplating the carbon-containing copper layer comprises electroplating the carbon-containing copper layer to have a thickness ranging from about 50 angstrom to about 4000 angstrom. 3. The method of claim 1 , wherein electroplating the second copper layer comprises electroplating the second copper layer to have a top surface which is spaced from a top surface of the carbon-containing copper layer at a first distance greater than or equal to about 1000 angstrom. 4. The method of claim 1 , wherein electroplating the carbon-containing copper layer comprises electroplating the carbon-containing copper layer to have a bottom surface which is spaced from a bottom surface of the first copper layer at a second distance greater than or equal to about 1000 angstrom. 5. The method of claim 1 , wherein a ratio of the carbon concentration of the carbon-containing copper layer to the carbon concentration of the first copper layer or the carbon concentration of the second copper layer is greater than about 1.5. 6. The method of claim 1 , wherein electroplating the carbon-containing copper layer comprises introducing an accelerator, a suppressor, and a leveling agent into the first plating tank to deposit the carbon-containing copper layer, wherein a concentration of the suppressor ranges from about 3M to about 8M, and a concentration of the leveling agent ranges from about 2M to about 10M. 7. The method of claim 1 , wherein electroplating the carbon-containing copper layer comprises introducing an accelerator, a suppressor, and a leveling agent into the first plating tank to deposit the carbon-containing copper layer, wherein a ratio of concentrations of the accelerator, the suppressor, and the leveling agent introduced in depositing the carbon-containing copper layer is about 6: 3: 2. 8. The method of claim 7 , wherein electroplating the first copper layer or the second copper layer comprises introducing the accelerator, the suppressor, and the leveling agent into the second plating tank to deposit the first copper layer or the second copper layer, wherein a ratio of concentrations of the accelerator, the suppressor and the leveling agent introduced in depositing the first copper layer or the second copper layer is about 6: 1.5: 1. 9. A method for manufacturing a copper layer structure, comprising: depositing a dielectric layer over a substrate, wherein the dielectric layer comprises a via hole and a trench over the via hole; and electroplating at least two copper layers, and at least one carbon-containing copper layer to separate the at least two copper layers from each other, wherein the copper layers and the carbon-containing copper layer are in contact with the dielectric layer, wherein a lowest one of the at least two copper layers fills the via hole, and a top one of the at least two copper layers fills an upper portion of the trench, wherein a carbon concentration of the at least one carbon-containing copper layer is greater than a carbon concentration of each of the at least two copper layers, and the carbon concentrations of the at least two copper layers are the same to each other. 10. The method of claim 9 , wherein a lowest one of the at least one carbon-containing copper layer fills a portion of the trench, and the lowest one of the at least one carbon-containing copper layer is disposed on the lowest one of the at least two copper layers. 11. The method of claim 9 , wherein the number of the at least one carbon-containing copper layer is more than one, the carbon-containing copper layers are separated from each other, and the number of the at least two copper layers is equal to the number of the at least one carbon-containing copper layer plus one. 12. The method of claim 11 , wherein a gap between any adjacent two of the carbon-containing copper layers is greater than or equal to about 4000 angstrom. 13. The method of claim 9 , wherein a ratio of the carbon concentration of the at least one carbon-containing copper layer to the carbon concentration of each of the at least two copper layers is greater than about 1.5. 14. The method of claim 9 , wherein electroplating the at least one carbon-containing copper layer comprises introducing an accelerator, a suppressor, and a leveling agent into a plating tank to plate the at least one carbon-containing copper layer, wherein a concentration of the suppressor ranges from about 3M to about 8M, and a concentration of the leveling agent ranges from about 2M to about 10M. 15. The method of claim 9 , wherein electroplating the at least one carbon-containing copper layer comprises introducing an accelerator, a suppressor, and a leveling agent into a first plating tank to plate the at least one carbon-containing copper layer, wherein a ratio of concentrations of the accelerator, the suppressor, and the leveling agent introduced in plating the at least one carbon-containing copper layer is about 6: 3: 2; and electroplating each of the at least two copper layers comprises introducing the accelerator, the suppressor, and the leveling agent into a second plating tank to plate each of the at least two copper layers, wherein a ratio of concentrations of the accelerator, the suppressor, and the leveling agent introduced in plating each of the at least two copper layers is about 6: 1.5: 1. 16. A method for forming a copper layer structure, comprising: providing a substrate comprising a circuit layer and a dielectric layer stacked on the circuit layer, wherein the dielectric layer has a via hole and a trench that is disposed over and communicates with the via hole, the via hole and the trench pass through the dielectric layer to expose a portion of the circuit layer, the trench comprises a first portion, a second portion, and a third portion sequentially located over the via hole, and the first, second, and third portions of the trench are wider than the via hole; electroplating a first copper layer filling the via hole and said first portion to form a via in the via hole, wherein electroplating the first copper layer is performed using a first concentration of a suppressor; electroplating a carbon-containing

Assignees

Inventors

Classifications

  • Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

  • by filling conductive material into holes, grooves or trenches · CPC title

  • Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

  • Carbon or carbon-containing materials, e.g. graphene · CPC title

  • Copper alloys · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10840184B2 cover?
In a method for manufacturing an interconnect structure, a dielectric layer is removed to form a first recess and a second recess. The first recess is below the second recess. A first metal layer is deposited to fill the first recess and a first portion of the second recess. A carbon-containing layer is deposited over the first metal layer to fill a second portion of the second recess, which is…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W20/425. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 17 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).