Pre-treatment composition before etching SiGe and method of fabricating semiconductor device using the same

Patent metadata

Field	Value
Publication number	US-10837115-B2
Application number	US-201816139506-A
Country	US
Kind code	B2
Filing date	Sep 24, 2018
Priority date	Mar 15, 2018
Publication date	Nov 17, 2020
Grant date	Nov 17, 2020

Abstract

A pre-treatment composition for use before etching SiGe includes an acid, an alcohol, and a silane compound having a chemical formula R—Si(R1)n(OR2)3-n in which R is (C3-C20)alkyl, (C6-C12)aryl, (C6-C12)aryl(C3-C20)alkyl, or (C3-C20)alkyl(C6-C12)aryl, R1 is hydrogen, hydroxyl, halogen, (C1-C20)alkyl, halo(C1-C20)alkyl, (C6-C12)aryl, (C6-C12)aryl(C1-C20)alkyl, or (C1-C20)alkyl(C6-C12)aryl, R2 is hydrogen, (C1-C20)alkyl, halo(C1-C20)alkyl, (C6-C12)aryl, (C6-C12)aryl(C1-C20)alkyl, or (C1-C20)alkyl(C6-C12)aryl, n is an integer of 0 to 2, and the alkyl, aryl, arylalkyl, or alkylaryl of R, and the alkyl, haloalkyl, aryl, arylalkyl, or alkylaryl of R1 may be further substituted with at least one substituent selected from halogen, hydroxyl, —N(R11)(R12), and —S(R13), where each of the R11, the R12 and the R13 is independently hydrogen or (C1-C20)alkyl.

First claim

What is claimed is:

1. A pre-treatment composition for use before etching SiGe, the composition consisting essentially of:
sulfuric acid in an amount of about 0.01 wt % to about 0.1 wt %;
isopropyl alcohol in an amount of about 1 wt % to about 80 wt %;
a silane compound represented by one of the following Formulae (1-1), (1-2), (1-3), (1-4), (1-5), (1-6) or (1-7) in an amount of about 0.01 wt % to 0.9 wt %; and
de-ionized water in an amount of greater than 19 wt % to about 98.98 wt %,
all wt % being based on a total weight of the composition,

2. The pre-treatment composition as claimed in claim 1 , wherein the silane compound represented by one of Formulae (1-1), (1-2), (1-3), or (1-7),

3. A method of fabricating a semiconductor device, the method comprising:
forming an insulation pattern, a silicon pattern, and a SiGe pattern on a semiconductor substrate;
supplying the pre-treatment composition as claimed in claim 1 to form a passivation layer on the insulation pattern; and
etching the SiGe pattern using a SiGe etching composition.

4. The method as claimed in claim 3 , further comprising performing heating or light irradiation to the passivation layer to increase bonding force between the passivation layer and the insulation pattern.

5. The method as claimed in claim 3 , further comprising performing heating of the passivation layer at a temperature of about 70° C. to about 200° C. for about 0.1 minutes to about 30 minutes to increase bonding force between the passivation layer and the insulation pattern, or performing light irradiation to the passivation layer with a wavelength of about 100 nm to about 400 nm for about 0.1 minutes to about 30 minutes to increase bonding force between the passivation layer and the insulation pattern.

6. The method as claimed in claim 3 , wherein the SiGe etching composition removes the passivation layer.

7. The method as claimed in claim 3 , wherein the SiGe etching composition includes an acid, an oxidant, and de-ionized water.

8. The method as claimed in claim 7 , wherein the SiGe etching composition further includes a surfactant.

9. The method as claimed in claim 1 , wherein:
the forming of the insulation pattern, the silicon pattern, and the SiGe pattern on the semiconductor substrate includes:
sequentially stacking a SiGe layer and a silicon layer on a semiconductor substrate;
pattering the silicon layer and the SiGe layer to form a trench that exposes the semiconductor substrate, and to form the silicon pattern and the SiGe pattern; and
forming the insulation pattern for partially filling the trench and exposing side walls of the silicon pattern and the SiGe pattern, and

the etching of the SiGe pattern includes removing the SiGe pattern to expose a bottom surface of the silicon pattern and a top surface of the semiconductor substrate.

10. The method as claimed in claim 9 , wherein the insulation pattern includes silicon oxide.

Assignees

• Samsung Electronics Co Ltd
• Enf Technology Co Ltd

Inventors

• Kim Soojin
• Lee Hyo-Sun
• Oh Jung-Min
• Lee Hyosan
• Kim Donghyun
• Kim Haksoo
• Oh Jung Jae
• Lee Myung Ho

Classifications

• H10P50/264

  by chemical means · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title