Methods and circuits for suppressing quantization noise in digital-to-analog converters

Patent metadata

Field	Value
Publication number	US-10833697-B2
Application number	US-201916558796-A
Country	US
Kind code	B2
Filing date	Sep 3, 2019
Priority date	Sep 6, 2018
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

Circuits and methods for converting digital input signals into the analog domain are described. Such circuits may perform the conversion in a segmented fashion. For example, a circuit may include a most significant bit (MSB) path and a least significant bit (LSB) path. The MSB path may include a first delta-sigma modulator having first and second outputs and a first digital-to-analog converter coupled to the first output of the first delta-sigma modulator. The LSB path comprises a second delta-sigma modulator comprising a loop filter and a quantizer. The quantizer may have an input coupled to the loop filter and to the digital filter. The LSB path may further include a second digital-to-analog converter coupled to an output of the quantizer. The circuit may further include a digital filter and/or a gain stage interposed between the MSB path and the LSB path.

First claim

What is claimed is:

1. A circuit comprising:
a most significant bit (MSB) path comprising:
a first delta-sigma modulator having first and second outputs; and
a first digital-to-analog converter coupled to the first output of the first delta-sigma modulator;

a digital filter coupled to the second output of the first delta-sigma modulator; and
a least significant bit (LSB) path comprising:
a second delta-sigma modulator comprising a loop filter and a quantizer, the quantizer having an input coupled to the loop filter and to the digital filter; and
a second digital-to-analog converter coupled to an output of the quantizer.

2. The circuit of claim 1 , wherein the first delta-sigma modulator comprises a first quantizer,
wherein the first output of the first delta-sigma modulator is an output of the first quantizer, and
wherein the quantizer is a second quantizer.

3. The circuit of claim 2 , wherein the second output of the first delta-sigma modulator is derived from the output of the first quantizer.

4. The circuit of claim 2 , wherein the first delta-sigma modulator further comprises a first loop filter, a first adder and a second adder,
wherein the first adder is coupled to an input of the first quantizer, the second adder is coupled to the output of the first quantizer and the first loop filter is coupled between the first adder and the second adder, and
wherein the loop filter is a second loop filter.

5. The circuit of claim 4 , wherein the second output of the first delta-sigma modulator is an output of the second adder.

6. The circuit of claim 1 , wherein the second digital-to-analog converter has less inputs than the first digital-to-analog converter.

7. The circuit of claim 1 , further comprising an amplifier coupled to the digital filter.

8. A circuit comprising:
a most significant bit (MSB) path comprising:
a first delta-sigma modulator having first and second outputs; and
a first digital-to-analog converter coupled to the first output of the first delta-sigma modulator;

an amplifier coupled to the second output of the first delta-sigma modulator; and
a least significant bit (LSB) path comprising:
a second delta-sigma modulator comprising a loop filter and a quantizer, the quantizer having an input coupled to the loop filter and to the amplifier; and
a second digital-to-analog converter coupled to an output of the quantizer.

9. The circuit of claim 8 , wherein the first delta-sigma modulator comprises a first quantizer,
wherein the first output of the first delta-sigma modulator is an output of the first quantizer, and
wherein the quantizer is a second quantizer.

10. The circuit of claim 9 , wherein the first delta-sigma modulator further comprises a first loop filter, a first adder and a second adder,
wherein the first adder is coupled to an input of the first quantizer, the second adder is coupled to the output of the first quantizer and the first loop filter is coupled between the first adder and the second adder, and
wherein the loop filter is a second loop filter.

11. The circuit of claim 10 , wherein the second output of the first delta-sigma modulator is an output of the second adder.

12. The circuit of claim 8 , wherein the second digital-to-analog converter has less inputs than the first digital-to-analog converter.

13. The circuit of claim 8 , wherein the second delta-sigma modulator further comprises a first adder and a second adder,
wherein the first adder is coupled to the input of the quantizer, the second adder is coupled to the output of the quantizer and the loop filter is coupled between the first adder and the second adder.

14. A method for controlling a digital-to-analog converter (DAC) having a plurality of switches, the method comprising:
processing an input digital signal with a delta-sigma modulator; and
generating, based on the processed input digital signal, a control signal comprising N control bits, each one of the N control bits being configured to control a respective switch of the plurality of switches of the DAC, wherein:
the generating comprises toggling, in each of a plurality of clock cycles, a same number of control bits of the N control bits from a first value to a second value, the number being less than N, and
the toggling comprises setting a threshold value.

15. The method of claim 14 , further comprising generating a plurality of state signals based on the processed input digital signal and generating the N control bits based on the plurality of state signals, wherein toggling the same number of control bits comprises toggling a subset of the N control bits corresponding to respective state signals that exceed the threshold value or are below the threshold value.

16. The method of claim 15 , wherein setting the threshold value comprises performing a search algorithm.

17. The method of claim 16 , wherein performing the search algorithm comprises varying the threshold value until a predefined number of the plurality of state signals exceeds or is below the threshold value.

18. The method of claim 15 , wherein the plurality of state signals exhibit triangular waves.

19. The method of claim 14 , wherein generating, based on the processed input digital signal, the control signal comprises providing the processed input digital signal to a quantizer and to an adder.

20. The method of claim 14 , wherein processing the input digital signal with the delta-sigma modulator comprises processing the input digital signal with a second order delta-sigma modulator.

Assignees

• Mediatek Singapore Pte Ltd

Inventors

• Shabra Ayman
• Ho Stacy
• Ashburn Jr Michael A

Classifications

• H03M3/338

  by permutation in the time domain, e.g. dynamic element matching (in multiple bit sub-converters H03M1/066) · CPC title

• H03M3/50

  Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M7/3004) · CPC title

• H03M3/324

  characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement · CPC title

• H03M3/30

  Delta-sigma modulation · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title