Delta sigma patterns for calibrating a digital-to-analog converter

Patent metadata

Field	Value
Publication number	US-9577657-B1
Application number	US-201615144163-A
Country	US
Kind code	B1
Filing date	May 2, 2016
Priority date	May 2, 2016
Publication date	Feb 21, 2017
Grant date	Feb 21, 2017

Abstract

A digital to analog converter (DAC) maps a digital word to an analog output. The DAC bits may have amplitude and timing errors. These errors (or sometimes referred herein as “non-idealities”) result in distortion and degradation of the dynamic range in DACs. To reduce these negative effects, delta-sigma patterns can be provided to two bit cells, a reference bit cell and a bit cell under calibration, to perform, e.g., amplitude calibration and timing skew calibration. Delta-sigma patterns are particularly advantageous over square wave signals, which cannot be scaled to perform amplitude calibration between bit cells having different bit weights and are limited in frequency to integer fractions of the sampling clock.

First claim

What is claimed is:

1. A method for measuring non-idealities of a digital-to-analog converter (DAC) having a plurality of DAC cells whose outputs are summed to generate an analog output of the DAC, the method comprising:
generating a first test signal corresponding to a weight of a first DAC cell and a second test signal corresponding to a weight of a second DAC cell;
encoding the first test signal and the second test signal into a first test input signal and a second test input signal respectively; and
providing the first test input signal and the second test input signal to the first DAC cell and the second DAC cell.

2. The method of claim 1 , wherein generating the first test signal and the second test signal comprises:
multiplying a test signal by a ratio of the weight of the second DAC cell and the weight of the first DAC cell to generate the first test signal; and
inverting the test signal to generate the second test signal.

3. The method of claim 1 , wherein the first test signal and the second test signal are generated by digitally scaling a test signal according to the weight of the first DAC cell and the weight of the second DAC cell.

4. The method of claim 1 , wherein encoding the first test signal and the second test signal comprises:
encoding the first test signal and the second test signal as two-level bit streams.

5. The method of claim 1 , wherein encoding the first test signal and the second test signal comprises:
converting the first test signal and the second test signal into the first test input signal and the second test input signal respectively using delta-sigma modulation.

6. The method of claim 1 , wherein encoding the first test signal and the second test signal comprises:
lowering bit-depth of the first test signal and the second test signal to generate the first test input signal and the second test input signal.

7. The method of claim 1 , wherein the first test signal and the second test signal each comprises a sine wave.

8. The method of claim 1 , further comprising:
measuring an amplitude error of the second DAC cell with respect to the first DAC cell by observing the analog output of the DAC or respective outputs of the first DAC cell and the second DAC cell.

9. The method of claim 1 , further comprising:
measuring timing skew of the second DAC cell with respect to the first DAC cell by observing the analog output of the DAC or respective outputs of the first DAC cell and the second DAC cell.

10. The method of claim 1 , further comprising:
measuring duty cycle error of the second DAC cell with respect to the first DAC cell by observing the analog output of the DAC or respective outputs of the first DAC cell and the second DAC cell.

11. A system for measuring non-idealities of a digital-to-analog converter (DAC) having a plurality of DAC cells whose outputs are summed to generate an analog output of the DAC, the system comprising:
a test signal generator to scale a test signal with a first multiplicative factor and to scale the test signal with a second multiplicative factor to generate a first test signal and a second test signal respectively;
a first noise shaper to process the first test signal and generate a first test input signal; and
a second noise shaper to process the second test signal and generate a second test input signal;
wherein the first test input signal and the second test input signal are provided as input to a first DAC cell and a second DAC cell.

12. The system of claim 11 , wherein the first multiplicative factor comprises a ratio of a bit weight of the second DAC cell and a bit weight of the first DAC cell.

13. The system of claim 11 , wherein the first multiplicative factor and the second multiplicative factor each comprises a coefficient selected based on a dynamic range of the first and second noise shapers.

14. The system of claim 11 , wherein either the first multiplicative factor or the second multiplicative factor comprises a negative coefficient for inverting the test signal or a scaled version of the test signal.

15. The system of claim 11 , wherein the first noise shaper and the second noise shaper are delta sigma encoders.

16. The system of claim 11 , further comprising:
a circuit to observe the analog output of the DAC and measure an error of the second DAC cell with respect to the first DAC cell.

17. A digital-to-analog converter (DAC) comprising:
first DAC cell for generating a first analog output based on a first two-level input;
second DAC cell for generating a second analog output based on a second two-level input;
means for digitally generating the first two-level input and the second two-level input based on a test signal; and
means for sensing an error of the second DAC cell with respect to the first DAC cell in the analog output of the DAC.

18. The DAC of claim 17 , further comprising:
means for correcting the error in the second DAC cell.

19. The DAC of claim 17 , wherein the means for digitally generating the first two-level input and the second two-level input comprises:
means for scaling the test signal by a ratio of the weight of the second DAC cell and the weight of the first DAC cell to generate a first test signal;
means for inverting the test signal to generate a second test signal; and
means for encoding the first test signal and the second test signal as the first two-level input and the second two-level input respectively.

20. The DAC of claim 17 , further comprising:
means for combining at least the first analog output and the second analog output to generate the analog output of the DAC;
wherein:
the first DAC cell and second DAC cell have different bit weights; and
the first two-level input and the second two-level input comprises a 1-bit delta-sigma sine wave test signal.

21. A method for measuring non-idealities of a digital-to-analog converter (DAC) having a plurality of DAC cells whose outputs are summed to generate an analog output of the DAC, the method comprising:
receiving a first test input signal by a first DAC cell;
receiving a second test input signal by a second DAC cell, wherein the first test input signal and the second test input signal are encoded and generated based on a weight of the first DAC cell and a weight of the second DAC cell; and
measuring an error of the second DAC cell with respect to the first DAC cell based on outputs of the first DAC cell and the second DAC cell.

Assignees

• Analog Devices Inc

Inventors

• Clara Martin

Classifications

• H03M3/38 Primary

  Calibration · CPC title

• H03M1/1071

  Measuring or testing · CPC title

• H03M1/1009 Primary

  Calibration · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/109 Primary

  for DC performance, i.e. static testing (H03M1/1085 takes precedence) · CPC title