3D-microstrip branchline coupler

Patent metadata

Field	Value
Publication number	US-10832989-B2
Application number	US-201916583987-A
Country	US
Kind code	B2
Filing date	Sep 26, 2019
Priority date	Oct 16, 2015
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.

First claim

What is claimed:

1. A semiconductor structure, comprising:
a thinned wafer;
a coupler comprising: plural through silicon vias in the thinned wafer; and plural conductive lines connecting ones of the plural through silicon vias; and
a ground shield structure surrounding the coupler.

2. The semiconductor structure of claim 1 , wherein the ground shield structure comprises other through silicon vias and other conductive lines.

3. The semiconductor structure of claim 1 , further comprising insulator layers on the plural conductive lines on upper and lower surfaces of the thinned wafer.

4. The semiconductor structure of claim 1 , wherein the thinned wafer is a semiconductor wafer.

5. The semiconductor structure of claim 1 , wherein the thinned wafer is a silicon wafer.

6. The semiconductor structure of claim 1 , wherein the plural through silicon vias are respective ports of the coupler.

7. The semiconductor structure of claim 6 , wherein a first port of the respective ports is an input signal port.

8. The semiconductor structure of claim 7 , wherein the input signal port is split into two quadrature signals at a second port of the respective ports and a third port of the respective ports.

9. The semiconductor structure of claim 8 , wherein the two quadrature signals at the second port and the third port are of equal amplitude and with 90 phase difference.

10. The semiconductor structure of claim 1 , wherein the ground shield structure comprises other through silicon vias formed in the thinned wafer.

11. A semiconductor structure, comprising:
a coupler comprising: plural through silicon vias in a wafer; and plural conductive lines connecting ones of the plural through silicon vias; and
a ground shield structure surrounding the coupler.

12. The semiconductor structure of claim 11 , wherein the ground shield structure comprises other through silicon vias and other conductive lines.

13. The semiconductor structure of claim 11 , further comprising insulator layers on the plural conductive lines on upper and lower surfaces of the wafer.

14. The semiconductor structure of claim 11 , wherein the wafer is a semiconductor wafer.

15. The semiconductor structure of claim 11 , wherein the wafer is a silicon wafer.

16. The semiconductor structure of claim 11 , wherein the plural through silicon vias are respective ports of the coupler.

17. The semiconductor structure of claim 16 , wherein a first port of the respective ports is an input signal port.

18. The semiconductor structure of claim 17 , wherein the input signal port is split into two quadrature signals at a second port of the respective ports and a third port of the respective ports.

19. The semiconductor structure of claim 18 , wherein the two quadrature signals at the second port and the third port are of equal amplitude and with 90 phase difference.

20. The semiconductor structure of claim 11 , wherein the ground shield structure comprises other through silicon vias formed in the wafer.

Assignees

• IBM

Inventors

• Dewitt Barbara S
• Mina Essam
• Rahman B M Farid
• Wang Guoan

Classifications

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01P3/003 Primary

  Coplanar lines · CPC title

• H01P3/026

  Coplanar striplines [CPS] · CPC title

• H01Q1/2283

  mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package · CPC title

• H01Q13/106

  Microstrip slot antennas (patch antenna elements H01Q9/0407) · CPC title