3D-microstrip branchline coupler

Patent metadata

Field	Value
Publication number	US-9780429-B2
Application number	US-201514885393-A
Country	US
Kind code	B2
Filing date	Oct 16, 2015
Priority date	Oct 16, 2015
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.

First claim

What is claimed:

1. A structure comprising:
a plurality of through silicon vias; and
conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias, wherein:
a first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler;
a second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler;
a third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler; and
a fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.

2. The structure of claim 1 , wherein the first port is an input signal port.

3. The structure of claim 2 , wherein the input signal port is split into two quadrature signals at the second port and the third port.

4. The structure of claim 3 , wherein the two quadrature signals at the second port and the third port are of equal amplitude and with 90 phase difference.

5. The structure of claim 3 , wherein the second port is 0.707 Vin<−90° and the second port is 0.707 Vin<−180°.

6. The structure of claim 5 , wherein the fourth port is isolated from the input signal port.

7. The structure of claim 1 , further comprising a ground shield surrounding the 3D branchline coupler.

8. The structure of claim 7 , wherein the ground shield includes a plurality of through silicon vias electrically connected by conductive lines.

9. The structure of claim 7 , wherein the conductive lines of the ground shield are coplanar with the conductive lines electrically connected to the upper portion and the lower portion of respective ones of the plurality of through silicon vias of the 3D branchline coupler.

10. The structure of claim 1 , wherein the conductive lines electrically connected to the first end and the second end of respective ones of the plurality of through silicon vias of the 3D branchline coupler are straight.

11. The structure of claim 1 , wherein the conductive lines electrically connected to the first end and the second end of respective ones of the plurality of through silicon vias of the 3D branchline coupler are meandering.

12. The structure of claim 1 , wherein:
a first of the conductive lines electrically connected to the first end of the first and third of the plurality of through silicon vias between the first port and the third port;
a second of the conductive lines are connected to the first end of the second and fourth of the plurality of through silicon vias between the second port and the fourth port;
a third of the conductive lines are connected to the second end of the first and second of the plurality of through silicon vias; and
a fourth of the conductive lines are connected to the second end of the third and fourth of the plurality of through silicon vias.

13. A structure comprising:
a first through silicon via forming a first port of a three dimensional (3D) branchline coupler;
a second through silicon via forming a second port of the 3D branchline coupler;
a third through silicon via forming a third port of the 3D branchline coupler;
a fourth through silicon via forming a fourth port of the 3D branchline coupler;
a first conductive line electrically connected to a first end of the first and third of the plurality of through silicon vias between a first port and a third port;
a second conductive line connected to the first end of the second and fourth of the plurality of through silicon vias between a second port and a fourth port;
a third conductive line connected to a second end of the first and second of the plurality of through silicon vias; and
a fourth conductive line connected to the second end of the third and fourth of the plurality of through silicon vias.

14. The structure of claim 13 , wherein:
the first port is an input signal port;
the input signal port is split into two quadrature signals at the second port and the third port; and
the two quadrature signals at the second port and the third port are of equal amplitude and with 90 phase difference.

15. The structure of claim 14 , wherein the second port is 0.707 Vin<−90° and the third port is 0.707 Vin<−180°.

16. The structure of claim 14 , wherein at least the first and second conductive lines are meandering.

17. The structure of claim 14 , further comprising a ground shield surrounding the 3D branchline coupler.

18. The structure of claim 17 , wherein the ground shield includes a plurality of through silicon vias electrically connected by conductive lines, and wherein the conductive lines of the ground shield are coplanar with the conductive lines of the 3D branchline coupler.

19. A method, comprising:
forming a first through silicon via forming a first port of a three dimensional (3D) branchline coupler;
forming a second through silicon via forming a second port of the 3D branchline coupler;
forming a third through silicon via forming a third port of the 3D branchline coupler;
forming a fourth through silicon via forming a fourth port of the 3D branchline coupler;
forming a first conductive line electrically connected to a first end of the first and third of the plurality of through silicon vias between a first port and third port;
forming a second conductive line connected to the first end of the second and fourth of the plurality of through silicon vias between a second port and a fourth port;
forming a third conductive line connected to a second end of the first and second of the plurality of through silicon vias; and
forming a fourth conductive line connected to the second end of the third and fourth of the plurality of through silicon vias.

20. The method of claim 19 , further comprising forming a ground shield about the 3D branchline coupler.

Assignees

• IBM

Inventors

• Dewitt Barbara S
• Mina Essam
• Rahman B M Farid
• Wang Guoan

Classifications

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01P11/001

  Manufacturing waveguides or transmission lines of the waveguide type · CPC title

• H01P3/003 Primary

  Coplanar lines · CPC title

• H01P11/007

  Manufacturing frequency-selective devices (resonators H01P11/008) · CPC title

• H01Q1/2283

  mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package · CPC title