Field effect transistors having multiple effective work functions

Patent metadata

Field	Value
Publication number	US-2016005831-A1
Application number	US-201414320831-A
Country	US
Kind code	A1
Filing date	Jul 1, 2014
Priority date	Jul 1, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions.

First claim

What is claimed is:

1 . A semiconductor structure comprising:
a first gate dielectric straddling a first semiconductor material portion and containing a stack of an adjustment oxide layer including a silicate of a metal selected from alkaline earth metals, Group IIIB elements, and rare earth metals and a first high dielectric constant (high-k) gate dielectric including a dielectric metal oxide and having a dielectric constant greater than 8.0; a first gate electrode in contact with said first gate dielectric and containing a first metallic material layer in contact with said first high-k gate dielectric; a second gate electrode straddling a second semiconductor material portion and containing a stack of a semiconductor oxide layer and a second high-k gate dielectric, wherein said first high-k gate dielectric differs in composition from said second high-k gate dielectric by presence of oxygen deficiency in said first high-k gate dielectric; and a second gate electrode in contact with said second gate dielectric and containing a second metallic material layer in contact with said second high-k gate dielectric.

2 . The semiconductor structure of claim 1 , wherein said second high-k gate dielectric does not include said metal in said silicate.

3 . The semiconductor structure of claim 2 , wherein said first high-k gate dielectric includes said metal at a lesser concentration than said adjustment oxide layer.

4 . The semiconductor structure of claim 1 , wherein said first metallic material layer and said second metallic material layer differ from each other in at least one of thickness and composition.

5 . The semiconductor structure of claim 1 , further comprising a third gate dielectric straddling a semiconductor material stack and containing a stack of another adjustment oxide layer and a third high-k gate dielectric including said dielectric metal oxide, wherein said semiconductor material stack comprises a semiconductor shell structure embedding, having a different composition from, and in epitaxial alignment with, a third semiconductor material portion.

6 . The semiconductor structure of claim 5 , further comprising a third gate electrode in contact with said third gate dielectric and containing a layer of a metallic material having a same composition and thickness as said first metallic material layer and in contact with said third high-k gate dielectric.

7 . The semiconductor structure of claim 5 , further comprising a fourth gate dielectric straddling another semiconductor material stack and containing a stack of another semiconductor oxide layer and a fourth high-k gate dielectric having a same composition and thickness as said second high-k gate dielectric, wherein said another semiconductor material stack comprises another semiconductor shell structure embedding, having a different composition from, and in epitaxial alignment with, a fourth semiconductor material portion.

8 . The semiconductor structure of claim 1 , wherein said first high-k gate dielectric and said second high-k gate dielectric include dielectric metal oxides of a same metal.

9 . The semiconductor structure of claim 1 , wherein said first gate electrode further comprises another metallic material layer having a same composition and thickness as said second metallic material layer and in contact with said first metallic material layer.

10 . The semiconductor structure of claim 1 , wherein each of said first and second gate electrodes further comprises a conductive material in contact with said another metallic material layer and said second metallic material layer, respectively.

11 . A method of forming a semiconductor structure comprising:
forming at least a first semiconductor material portion and a second semiconductor material portion on a substrate; forming a first dielectric material stack over said first semiconductor material portion and a second dielectric material stack over said second semiconductor material portion, said first dielectric material stack comprising an adjustment oxide layer including a silicate of a metal selected from alkaline earth metals, Group IIIB elements, and rare earth metals and a first portion of a contiguous high dielectric constant (high-k) dielectric layer, and said second dielectric material stack comprising a semiconductor oxide layer and a second portion of said contiguous high-k dielectric layer; forming a first metallic material layer and a sacrificial capping layer on said high-k dielectric layer over said first and second dielectric material stacks; inducing oxygen deficiency in said contiguous high-k dielectric layer employing an anneal in which oxygen supply into said contiguous high-k dielectric layer is blocked by said sacrificial capping layer; physically exposing a top surface of said second portion of said contiguous high-k dielectric layer by removing a portion of said first metallic material layer, while a remaining portion of said first metallic material layer is present over said first semiconductor material portion; and forming a second metallic material layer directly on said top surface of said second portion of said contiguous high-k dielectric layer and a top surface of said first metallic material layer.

12 . The method of claim 11 , further comprising curing oxygen deficiency in said second portion of said contiguous high-k dielectric layer by exposing said top surface of said second portion of said contiguous high-k dielectric layer prior to formation of said second metallic material layer.

13 . The method of claim 11 , further comprising:
forming a stack including a layer of a semiconductor oxide material, said contiguous high-k dielectric layer, and a dielectric oxide material layer on said first and second semiconductor material portions, said layer of said semiconductor oxide material including said semiconductor oxide layer; and annealing said stack employing at least another sacrificial capping layer, wherein a material of said dielectric oxide material layer diffuses through said high-k dielectric layer into an underlying portion of said layer of said semiconductor oxide material to form said adjustment oxide layer.

14 . The method of claim 13 , further comprising removing a portion of said dielectric oxide material layer from above said second semiconductor material portion prior to formation of said at least another sacrificial capping layer.

15 . The method of claim 11 , further comprising depositing at least one conductive material directly on said second metallic material layer.

16 . The method of claim 15 , further comprising:
forming a planarization dielectric layer over said first semiconductor material portion and said second semiconductor material portion prior to formation of said first and second dielectric material stacks; and removing portions of said at least one conductive material and said first and second metallic material layers from above a horizontal plane including a top surface of said planarization dielectric layer.

17 . The method of claim 11 , further comprising:
forming a third semiconductor material portion comprising a same material as said first and second semiconductor material portions on said substrate; forming a semiconductor shell structure on said third semiconductor material portion by selective epitaxial deposition of a semiconductor material having a different composition than said third semiconductor material portion; and forming a third dielectric material stack having a same composition as said first dielectric material stack over said third semicondu

Assignees

• IBM

Inventors

• Ando Takashi
• Dai Min
• Kannan Balaji
• Krishnan Siddarth A
• Kwon Unoh

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title

• H10D84/0158

  the components including FinFETs · CPC title