Insulator semiconductor device-structure

Patent metadata

Field	Value
Publication number	US-10832920-B2
Application number	US-201916269794-A
Country	US
Kind code	B2
Filing date	Feb 7, 2019
Priority date	Sep 6, 2016
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

A semiconductor device includes a semiconductor substrate, a first semiconductor layer on the semiconductor substrate and having an exposed portion of a lower surface, a capping layer on the first semiconductor layer, a second semiconductor layer below the capping layer and having a side surface substantially in full contact with the capping layer, a cavity defined by the first semiconductor layer, the second semiconductor layer, and the capping layer, and a through-hole passing through the capping layer and the second semiconductor layer and extending to the cavity.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a first semiconductor layer on the semiconductor substrate and having an exposed portion of a lower surface;
a capping layer on the first semiconductor layer and the capping layer being in contact with the first semiconductor layer;
a second semiconductor layer below the capping layer and having a rounded off surface substantially in full contact with the capping layer;
a cavity defined by the first semiconductor layer, the second semiconductor layer, and the capping layer; and
a through-hole passing through the capping layer and the second semiconductor layer and extending to the cavity.

2. The semiconductor device of claim 1 , wherein the through-hole comprises:
a first through-hole passing the second semiconductor layer; and
a second through-hole passing the capping layer and aligned with the first through-hole.

3. The semiconductor device of claim 1 , wherein the first and second semiconductor layers each comprise polysilicon; and the capping layer comprise silicon nitride.

4. The semiconductor device of claim 1 , further comprising:
a first recess in the capping layer extending to the first semiconductor layer; and
a second recess in the capping layer extending to the second semiconductor layer.

5. The semiconductor device of claim 4 , further comprising:
a first contact layer on a bottom of the first recess; and
a second contact layer on a bottom and sidewalls of the second recess and extending over an upper surface of the capping layer.

6. The semiconductor device of claim 5 , wherein the first and second contact layers each comprise aluminum, copper, or tungsten.

7. The semiconductor device of claim 1 , further comprising a third recess exposing a lower surface portion of the first semiconductor layer.

8. The semiconductor device of claim 7 , wherein the third recess has sidewalls that are substantially perpendicular to the first semiconductor layer.

9. The semiconductor device of claim 1 , wherein the cavity has a rounded off edge formed by a portion of the capping layer.

10. The semiconductor device of claim 9 , wherein the rounded off edge of the cavity is adjacent to the rounded off surface of the second semiconductor layer.

11. The semiconductor device of claim 1 , wherein the first semiconductor layer has a portion permanently attached to the semiconductor substrate.

12. The semiconductor device of claim 5 , wherein the first contact layer is formed on sidewalls of the first recess and extending to an upper surface of the capping layer.

13. The semiconductor device of claim 1 , wherein the capping layer is in direct contact with the substrate.

Assignees

• Semiconductor Mfg Int Beijing Corp
• Semiconductor Mfg Int Shanghai Corp

Inventors

• Wang Xianchao

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10W70/68

  Shapes or dispositions thereof · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10P14/6516

  of treatments performed after formation of the materials · CPC title