Method for preventing excessive etching of edges of an insulator layer

Patent metadata

Field	Value
Publication number	US-10249508-B2
Application number	US-201715679937-A
Country	US
Kind code	B2
Filing date	Aug 17, 2017
Priority date	Sep 6, 2016
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a first insulator layer on the first semiconductor layer, forming a patterned second semiconductor layer on the first insulator layer, the patterned second semiconductor layer having an actual thickness greater than a target thickness and exposing a portion of the first insulator layer; forming a second insulator layer as a spacer on the exposed portion of the first insulator layer, and performing an etching process on the patterned second semiconductor layer until the second semiconductor layer has the target thickness and concurrently removing the second insulator layer. The method can eliminate capillary etching of the spacer in a subsequent removal of the first insulator layer.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
forming a first semiconductor layer on a semiconductor substrate;
forming a first insulator layer on the first semiconductor layer exposing an edge portion of the first semiconductor layer;
forming a patterned second semiconductor layer on the first insulator layer, the patterned second semiconductor layer having an actual thickness greater than a target thickness and exposing a portion of the first insulator layer;
forming a second insulator layer as a spacer on the exposed portion of the first insulator layer;
performing an etching process on the patterned second semiconductor layer until the second semiconductor layer has the target thickness and concurrently removing the second insulator layer.

2. The method of claim 1 , wherein the actual thickness is 30% to 50% greater than the target thickness.

3. The method of claim 1 , wherein the actual thickness is in a range between 0.45 um and 0.6 um, and the target thickness is in a range between 0.3 um and 0.4 um.

4. The method of claim 1 , wherein the first and second semiconductor layers each comprises polysilicon; and the first and second insulator layers each comprise silicon oxide.

5. The method of claim 1 , wherein the exposed portion of the first insulator layer comprises an edge portion.

6. The method of claim 1 , wherein the patterned second semiconductor layer comprises a first through-hole extending through the second semiconductor layer to a surface of the first insulator layer.

7. The method of claim 6 , further comprising:
forming a capping layer on the first semiconductor layer, the first insulator layer, and the second semiconductor layer, the capping layer having a material different from a material of the first insulator layer.

8. The method of claim 7 , wherein the capping layer comprises silicon nitride.

9. The method of claim 7 , further comprising:
forming a first recess exposing a surface portion of the first semiconductor layer, a second recess exposing a surface portion of the second semiconductor layer, and a second through-hole aligned with the first through-hole, the first and second through-holes collectively forming a through-hole passing through the capping layer and the second semiconductor layer and extending to the first insulator layer.

10. The method of claim 9 , further comprising:
forming a first contact layer on a bottom of the first recess; and
forming a second contact layer on a bottom and sidewalls of the second recess and extending on an upper layer of the capping layer.

11. The method of claim 10 , wherein the first and second contact layers each comprise aluminum, copper, or tungsten.

12. The method of claim 11 , further comprising:
performing an etching process on the semiconductor substrate to form a third recess exposing a portion of a lower surface of the first semiconductor layer.

13. The method of claim 12 , further comprising:
removing the first insulator layer to form a cavity that is defined by the first semiconductor layer, the second semiconductor layer, and the capping layer.

14. The method of claim 1 , wherein performing the etching process on the patterned second semiconductor layer comprises rounding off an edge of the second semiconductor layer and a portion of an edge of the first insulator layer.

15. The method of claim 1 , wherein performing the etching process on the patterned second semiconductor layer comprises rounding off an edge of the first insulator layer.

16. The method of claim 14 , further comprising:
forming a capping layer on the first semiconductor layer, the first insulator layer, and the second semiconductor layer, the capping layer having a material different from a material of the first insulator layer.

17. The method of claim 16 , wherein a shape of an outer edge of the capping layer conforms to the rounded off edge of the second semiconductor layer and the rounded off portion of the edge of the first insulator layer.

Assignees

• Semiconductor Mfg Int Beijing Corp
• Semiconductor Mfg Int Shanghai Corp

Inventors

• Wang Xianchao

Classifications

• B81C1/00587 Primary

  Processes for avoiding or controlling over-etching not provided for in B81C1/00571 - B81C1/00579 · CPC title

• B81B2203/0127

  Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function · CPC title

• B81B2201/0257

  Microphones or microspeakers · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title